4e8d2d1593
src/arch/isa_parser.py:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/operands.isa:
src/base/bigint.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/mem/packet_access.hh:
make ldtw(a) Twin 32 bit load work correctly
--HG--
extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
89 lines
2.9 KiB
C++
89 lines
2.9 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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*/
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#include "arch/isa_traits.hh"
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#include "base/bigint.hh"
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#include "mem/packet.hh"
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#include "sim/byteswap.hh"
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#ifndef __MEM_PACKET_ACCESS_HH__
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#define __MEM_PACKET_ACCESS_HH__
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// The memory system needs to have an endianness. This is the easiest
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// way to deal with it for now. At some point, we will have to remove
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// these functions and make the users do their own byte swapping since
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// the memory system does not in fact have an endianness.
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template<>
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inline Twin64_t
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Packet::get()
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{
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Twin64_t d;
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assert(staticData || dynamicData);
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assert(sizeof(Twin64_t) <= size);
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d.a = TheISA::gtoh(*(uint64_t*)data);
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d.b = TheISA::gtoh(*((uint64_t*)data + 1));
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return d;
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}
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template<>
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inline Twin32_t
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Packet::get()
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{
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Twin32_t d;
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assert(staticData || dynamicData);
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assert(sizeof(Twin32_t) <= size);
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d.a = TheISA::gtoh(*(uint32_t*)data);
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d.b = TheISA::gtoh(*((uint32_t*)data + 1));
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return d;
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}
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/** return the value of what is pointed to in the packet. */
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template <typename T>
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inline T
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Packet::get()
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{
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assert(staticData || dynamicData);
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assert(sizeof(T) <= size);
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return TheISA::gtoh(*(T*)data);
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}
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/** set the value in the data pointer to v. */
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template <typename T>
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inline void
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Packet::set(T v)
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{
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assert(sizeof(T) <= size);
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*(T*)data = TheISA::htog(v);
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}
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#endif //__MEM_PACKET_ACCESS_HH__
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