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isa
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Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-06-19 18:54:40 -07:00 |
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linux
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Ignore "time" and "times" syscalls.
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2007-03-20 23:53:52 -04:00 |
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solaris
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Implement current working directory for LiveProcesses
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2006-11-16 12:43:11 -08:00 |
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arguments.cc
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Replaced getArg with a SPARC implementation.
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2006-11-08 00:32:04 -05:00 |
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arguments.hh
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implement vtophys and 32bit gdb support
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2007-02-18 19:57:46 -05:00 |
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asi.cc
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Panic if any CMT registers are accessed
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2007-03-08 21:49:13 -05:00 |
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asi.hh
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Panic if any CMT registers are accessed
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2007-03-08 21:49:13 -05:00 |
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faults.cc
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Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures.
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2007-03-07 20:04:46 +00:00 |
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faults.hh
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Make name, isMachineCheckFault, and isAlignmentFault const.
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2007-07-18 16:09:00 -07:00 |
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floatregfile.cc
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fix mostly floating point related
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2007-02-02 18:04:42 -05:00 |
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floatregfile.hh
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Moved some constants from isa_traits.hh to the reg file headers.
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2006-11-22 23:49:44 -05:00 |
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handlers.hh
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Forgot to commit this new file last earlier.
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2007-03-02 14:43:27 +00:00 |
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interrupts.hh
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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intregfile.cc
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Make SPARC checkpointing work
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2007-01-30 18:25:39 -05:00 |
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intregfile.hh
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Fixed an off-by-one error.
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2007-03-08 00:55:16 -05:00 |
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isa_traits.hh
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Make the GSR into a renamed control register. It should be split into a renamed part and a control part for the different bitfields, but the renamed part is all that's actually used.
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2007-04-22 17:43:45 +00:00 |
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kernel_stats.hh
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Put kernel_stats back into arch.
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2006-11-07 22:34:34 -05:00 |
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locked_mem.hh
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Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
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2006-10-08 10:53:24 -07:00 |
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miscregfile.cc
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Assign traceData to be NULL at BaseSimpleCPU constructor.
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2007-05-31 16:01:41 -04:00 |
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miscregfile.hh
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implement ipi stufff for SPARC
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2007-03-09 16:56:39 -05:00 |
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mmaped_ipr.hh
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reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes)
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2006-12-04 19:39:57 -05:00 |
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pagetable.cc
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Make SPARC checkpointing work
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2007-01-30 18:25:39 -05:00 |
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pagetable.hh
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implement vtophys and 32bit gdb support
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2007-02-18 19:57:46 -05:00 |
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predecoder.hh
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Make branches work by repopulating the predecoder every time through. This is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though.
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2007-06-19 18:17:34 +00:00 |
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process.cc
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Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-05-09 22:04:58 -07:00 |
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process.hh
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Make trap instructions always generate TrapInstruction Fault objects which call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running.
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2007-02-28 16:36:38 +00:00 |
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regfile.cc
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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regfile.hh
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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remote_gdb.cc
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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remote_gdb.hh
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Fix up the remote gdb include gaurds so it doesn't use the same symbol as Alpha does.
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2007-03-05 14:46:49 +00:00 |
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SConscript
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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SConsopts
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Rework the way SCons recurses into subdirectories, making it
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2007-03-10 23:00:54 -08:00 |
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sparc_traits.hh
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Make the GSR into a renamed control register. It should be split into a renamed part and a control part for the different bitfields, but the renamed part is all that's actually used.
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2007-04-22 17:43:45 +00:00 |
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SparcSystem.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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SparcTLB.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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stacktrace.cc
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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stacktrace.hh
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Put the ProcessInfo and StackTrace objects into the ISA namespaces.
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2006-11-08 00:52:04 -05:00 |
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syscallreturn.hh
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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system.cc
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make our code a little more standards compliant
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2007-01-26 18:48:51 -05:00 |
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system.hh
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Initial work to make remote gdb available in SE mode. This is completely untested.
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2006-12-20 18:39:40 -05:00 |
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tlb.cc
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Panic if any CMT registers are accessed
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2007-03-08 21:49:13 -05:00 |
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tlb.hh
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implement vtophys and 32bit gdb support
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2007-02-18 19:57:46 -05:00 |
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tlb_map.hh
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fix smul and sdiv to sign extend, and handle overflow/underflow corretly
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2007-01-25 13:43:46 -05:00 |
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types.hh
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Make register indexes larger so they can actually hold all the legal values. Oops!
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2007-04-14 17:08:24 +00:00 |
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ua2005.cc
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fix interrupting during a quisce on sparc
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2007-03-13 00:05:52 -04:00 |
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utility.hh
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Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-03-15 02:52:51 +00:00 |
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vtophys.cc
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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vtophys.hh
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implement vtophys and 32bit gdb support
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2007-02-18 19:57:46 -05:00 |
