gem5/src/cpu/minor
Andreas Sandberg 48281375ee mem, cpu: Add a separate flag for strictly ordered memory
The Request::UNCACHEABLE flag currently has two different
functions. The first, and obvious, function is to prevent the memory
system from caching data in the request. The second function is to
prevent reordering and speculation in CPU models.

This changeset gives the order/speculation requirement a separate flag
(Request::STRICT_ORDER). This flag prevents CPU models from doing the
following optimizations:

    * Speculation: CPU models are not allowed to issue speculative
      loads.

    * Write combining: CPU models and caches are not allowed to merge
      writes to the same cache line.

Note: The memory system may still reorder accesses unless the
UNCACHEABLE flag is set. It is therefore expected that the
STRICT_ORDER flag is combined with the UNCACHEABLE flag to prevent
this behavior.
2015-05-05 03:22:33 -04:00
..
activity.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
activity.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
buffers.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
cpu.cc alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate 2014-09-20 17:18:35 -04:00
cpu.hh alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate 2014-09-20 17:18:35 -04:00
decode.cc arm: Fixes based on UBSan and static analysis 2014-11-14 03:53:51 -05:00
decode.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
dyn_inst.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
dyn_inst.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
exec_context.hh arch: Make readMiscRegNoEffect const throughout 2015-02-16 03:33:28 -05:00
execute.cc cpu: Work around gcc 4.9 issues with Num_OpClasses 2015-05-05 03:22:19 -04:00
execute.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
fetch1.cc mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
fetch1.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
fetch2.cc arm: Fixes based on UBSan and static analysis 2014-11-14 03:53:51 -05:00
fetch2.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
func_unit.cc arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
func_unit.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
lsq.cc mem, cpu: Add a separate flag for strictly ordered memory 2015-05-05 03:22:33 -04:00
lsq.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
MinorCPU.py cpu: re-organizes the branch predictor structure. 2015-04-13 17:33:57 -05:00
pipe_data.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
pipe_data.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
pipeline.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
pipeline.hh cpu: Probe points for basic PMU stats 2014-10-16 05:49:41 -04:00
SConscript cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
SConsopts arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
scoreboard.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
scoreboard.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
stats.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
stats.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
trace.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00