ac161c1d72
This patch takes the Linux thread info support scattered across different ISA implementations (currently in ARM, ALPHA, and MIPS), and unifies them into a single file. Adds a few more helper functions to read out TGID, mm, etc. ISA-specific information (e.g., ALPHA PCBB register) is now moved to the corresponding isa_traits.hh files.
90 lines
3.7 KiB
C++
90 lines
3.7 KiB
C++
/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_ISATRAITS_HH__
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#define __ARCH_X86_ISATRAITS_HH__
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#include "arch/x86/types.hh"
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#include "arch/x86/x86_traits.hh"
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#include "base/types.hh"
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namespace LittleEndianGuest {}
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namespace X86ISA
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{
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//This makes sure the little endian version of certain functions
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//are used.
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using namespace LittleEndianGuest;
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// X86 does not have a delay slot
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#define ISA_HAS_DELAY_SLOT 0
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// X86 NOP (XCHG rAX, rAX)
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//XXX This needs to be set to an intermediate instruction struct
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//which encodes this instruction
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//4k. This value is not constant on x86.
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const int LogVMPageSize = 12;
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const int VMPageSize = (1 << LogVMPageSize);
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const int PageShift = 12;
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const int PageBytes = 1ULL << PageShift;
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const int BranchPredAddrShiftAmt = 0;
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// Memory accesses can be unaligned
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const bool HasUnalignedMemAcc = true;
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const bool CurThreadInfoImplemented = false;
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const int CurThreadInfoReg = -1;
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const ExtMachInst NoopMachInst = {
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0x0, // No legacy prefixes.
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0x0, // No rex prefix.
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{ 1, 0x0, 0x0, 0x90 }, // One opcode byte, 0x90.
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0x0, 0x0, // No modrm or sib.
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0, 0, // No immediate or displacement.
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8, 8, 8, // All sizes are 8.
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0, // Displacement size is 0.
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SixtyFourBitMode // Behave as if we're in 64 bit
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// mode (this doesn't actually matter).
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};
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}
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#endif // __ARCH_X86_ISATRAITS_HH__
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