gem5/sim
Ali Saidi c27c122afc Add the bus and connector objects to scons
change getPort parameter from char* to string
Add an extra phase between construction and init called connect

SConscript:
    Add the bus and connector objects to scons
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    the connection to memory shouldn't be made until we know the memory
    object exists (e.g. after construction)
dev/io_device.hh:
    change to const string
mem/bus.hh:
    change getPort parameter from char* to string
    initialize num_interfaces
mem/mem_object.hh:
    change getPort parameter from char* to string
mem/physical.cc:
mem/physical.hh:
    change getPort parameter from char* to string
    get rid of the bus object I created last time
python/m5/objects/PhysicalMemory.py:
    get rid of the bus object I created last time
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
    Add an extra phase between construction and init called connect

--HG--
extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
2006-03-26 21:44:22 -05:00
..
async.hh Many files: 2005-06-05 05:16:00 -04:00
builder.cc Many files: 2005-06-05 05:16:00 -04:00
builder.hh Many files: 2005-06-05 05:16:00 -04:00
byteswap.hh An attempt to get byteswap to work accross more machines. 2006-03-17 14:11:14 -05:00
debug.cc Many files: 2005-06-05 05:16:00 -04:00
debug.hh Many files: 2005-06-05 05:16:00 -04:00
eventq.cc Many files: 2005-06-05 05:16:00 -04:00
eventq.hh Many files: 2005-06-05 05:16:00 -04:00
faults.cc Work towards factoring isa_traits.hh into smaller, more specialized files. 2006-03-10 19:11:27 -05:00
faults.hh Some clean up work with faults. 2006-03-07 04:31:38 -05:00
host.hh Moved MaxAddr. 2006-03-10 18:26:12 -05:00
main.cc Add the bus and connector objects to scons 2006-03-26 21:44:22 -05:00
param.cc fixes for gcc 4.0 2005-09-12 03:01:43 -04:00
param.hh Fixes to build with gcc 4.0. 2005-09-02 21:30:02 -04:00
process.cc add translations for new sections that are mmapped or when the brk 2006-03-15 17:04:50 -05:00
process.hh add translations for new sections that are mmapped or when the brk 2006-03-15 17:04:50 -05:00
pseudo_inst.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
pseudo_inst.hh Add quiesceNs, quiesceTime, quiesceCycles, and m5panic pseudo ops. 2006-02-28 18:41:04 -05:00
root.cc Convert type of max_time and progress_interval parameters 2005-09-01 11:32:58 -04:00
serialize.cc fix the MAX_CHECKPOINTS stuff 2005-09-18 21:20:24 -04:00
serialize.hh Many files: 2005-06-05 05:16:00 -04:00
sim_events.cc Move max_time and progress_interval parameters to the Root 2005-06-22 09:59:13 -04:00
sim_events.hh Move max_time and progress_interval parameters to the Root 2005-06-22 09:59:13 -04:00
sim_exit.hh Many files: 2005-06-05 05:16:00 -04:00
sim_object.cc Add the bus and connector objects to scons 2006-03-26 21:44:22 -05:00
sim_object.hh Add the bus and connector objects to scons 2006-03-26 21:44:22 -05:00
startup.cc Many files: 2005-06-05 05:16:00 -04:00
startup.hh Many files: 2005-06-05 05:16:00 -04:00
stat_control.cc Fix bug where simulation terminates same cycle as last stat dump causing a duplicate row in db 2005-11-02 14:45:35 -05:00
stat_control.hh Many files: 2005-06-05 05:16:00 -04:00
stats.hh Many files: 2005-06-05 05:16:00 -04:00
syscall_emul.cc steps toward making syscalls work 2006-03-18 10:51:28 -05:00
syscall_emul.hh add translations for new sections that are mmapped or when the brk 2006-03-15 17:04:50 -05:00
system.cc Replace Memory with MemObject; no need for two different levels of hierarchy there. 2006-03-12 17:21:59 -05:00
system.hh Replace Memory with MemObject; no need for two different levels of hierarchy there. 2006-03-12 17:21:59 -05:00
vptr.hh Changed targetarch to just arch. 2006-02-27 05:35:43 -05:00