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gem5/src/dev/x86
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Gabe Black 8bbfb1b39d x86: pc: Put a stub IO device at port 0xed which the kernel can use for delays. 
There was already a stub device at 0x80, the port traditionally used for an IO
delay. 0x80 is also the port used for POST codes sent by firmware, and that
may have prompted adding this port as a second option.
2014-11-21 17:22:02 -08:00
..
cmos.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
cmos.hh dev: make BasicPioDevice take size in constructor 2013-07-11 21:57:04 -05:00
Cmos.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
i8042.cc dev: make BasicPioDevice take size in constructor 2013-07-11 21:57:04 -05:00
i8042.hh dev: make BasicPioDevice take size in constructor 2013-07-11 21:57:04 -05:00
I8042.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
i8237.cc x86: Add checkpointing capability to devices 2011-02-06 22:14:18 -08:00
i8237.hh dev: make BasicPioDevice take size in constructor 2013-07-11 21:57:04 -05:00
I8237.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
i8254.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
i8254.hh dev: make BasicPioDevice take size in constructor 2013-07-11 21:57:04 -05:00
I8254.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
i8259.cc dev: make BasicPioDevice take size in constructor 2013-07-11 21:57:04 -05:00
i8259.hh dev: consistently end device classes in 'Device' 2013-07-11 21:56:50 -05:00
I8259.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
i82094aa.cc dev: make BasicPioDevice take size in constructor 2013-07-11 21:57:04 -05:00
i82094aa.hh dev: consistently end device classes in 'Device' 2013-07-11 21:56:50 -05:00
I82094AA.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
intdev.cc dev: consistently end device classes in 'Device' 2013-07-11 21:56:50 -05:00
intdev.hh mem: Rename Bus to XBar to better reflect its behaviour 2014-09-20 17:18:32 -04:00
pc.cc SE/FS: Remove System::platform and Platform::intrFrequency. 2011-09-30 00:29:07 -07:00
pc.hh SE/FS: Remove System::platform and Platform::intrFrequency. 2011-09-30 00:29:07 -07:00
Pc.py x86: pc: Put a stub IO device at port 0xed which the kernel can use for delays. 2014-11-21 17:22:02 -08:00
PcSpeaker.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
SConscript dev: consistently end device classes in 'Device' 2013-07-11 21:56:50 -05:00
south_bridge.cc includes: sort includes again 2009-05-17 14:34:52 -07:00
south_bridge.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
SouthBridge.py dev: seperate legacy io offsets from PCI offset 2014-09-03 07:43:06 -04:00
speaker.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
speaker.hh dev: make BasicPioDevice take size in constructor 2013-07-11 21:57:04 -05:00
X86IntPin.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00