Ron Dreslinski 1ccfdb442f Timing cache works for hello world test. ... Still need 1) detailed CPU (blocking ability in cache) 1a) Multiple outstanding requests (need to keep track of times for events) 2)Multi-level support 3)MP coherece support 4)LL/SC support 5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu)) src/cpu/simple/timing.cc: Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port. src/mem/cache/base_cache.cc: Handle marking MSHR's in service Add support for getting CSHR's src/mem/cache/base_cache.hh: Make these functions visible at the base cache level src/mem/cache/cache.hh: make the functions virtual src/mem/cache/cache_impl.hh: Rename the function to make sense src/mem/packet.hh: Accidentally clearing the needsResponse field when sending a response back. --HG-- extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2		2006-07-06 16:52:05 -04:00
..
arch	more steps toward O3 SMT	2006-07-06 11:25:44 -04:00
base	Fix up some merge problems.	2006-07-05 16:54:24 -04:00
cpu	Timing cache works for hello world test.	2006-07-06 16:52:05 -04:00
dev	Add default responder to bus	2006-07-06 14:41:01 -04:00
kern	Merge zizzer.eecs.umich.edu:/bk/newmem	2006-06-17 18:28:21 -04:00
mem	Timing cache works for hello world test.	2006-07-06 16:52:05 -04:00
python	Merge ktlim@zizzer:/bk/newmem	2006-07-06 14:54:09 -04:00
sim	Change the return value of drain. False means the object wasn't able to drain yet.	2006-07-06 13:57:21 -04:00
unittest	Merge iceaxe.:/Volumes/work/research/m5/head	2006-06-11 22:01:34 -04:00
Doxyfile	New directory structure:	2006-05-22 14:29:33 -04:00
SConscript	Remove sampler and serializer. Now they are handled through C++ interacting with Python.	2006-07-05 21:14:36 -04:00