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gem5/src/cpu/o3
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Andreas Sandberg 7eb0fb8b6e cpu: Check that the memory system is in the correct mode 
This patch adds checks to all CPU models to make sure that the memory
system is in the correct mode at startup and when resuming after a
drain.  Previously, we only checked that the memory system was in the
right mode when resuming. This is inadequate since this is a
configuration error that should be detected at startup as well as when
resuming. Additionally, since the check was done using an assert, it
wasn't performed when NDEBUG was set (e.g., the fast target).
2013-01-07 13:05:41 -05:00
..
base_dyn_inst.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
bpred_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
bpred_unit.hh O3: Track if the RAS has been pushed or not to pop the RAS if neccessary. 2012-06-29 11:18:29 -04:00
bpred_unit_impl.hh TournamentBP: Fix some bugs with table sizes and counters 2012-12-06 09:31:06 -06:00
checker.cc arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
checker.hh cpu: Add header files for checker CPUs 2012-11-02 11:32:01 -05:00
comm.hh O3: Pack the comm structures a bit better to reduce their size. 2012-09-25 11:49:40 -05:00
commit.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
commit.hh stats: remove duplicate instruction stats from the commit stage 2012-09-12 11:35:52 -04:00
commit_impl.hh cpu: rename the misleading inSyscall to noSquashFromTC 2013-01-07 13:05:33 -05:00
cpu.cc cpu: Check that the memory system is in the correct mode 2013-01-07 13:05:41 -05:00
cpu.hh arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
cpu_policy.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
decode.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
decode.hh Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
decode_impl.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
dep_graph.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
deriv.cc cpu: O3 add a header declaring the DerivO3CPU 2012-11-02 11:32:01 -05:00
deriv.hh cpu: O3 add a header declaring the DerivO3CPU 2012-11-02 11:32:01 -05:00
dyn_inst.cc O3: Generaize the O3 IMPL class so it isn't split out by ISA. 2008-10-09 00:10:02 -07:00
dyn_inst.hh cpu: rename the misleading inSyscall to noSquashFromTC 2013-01-07 13:05:33 -05:00
dyn_inst_impl.hh cpu: rename the misleading inSyscall to noSquashFromTC 2013-01-07 13:05:33 -05:00
fetch.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
fetch.hh Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
fetch_impl.hh Decoder: Remove the thread context get/set from the decoder. 2013-01-04 19:00:45 -06:00
free_list.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
free_list.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
fu_pool.cc Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
fu_pool.hh Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
FuncUnitConfig.py CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
FUPool.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
iew.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
iew.hh Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
iew_impl.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
impl.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
inst_queue.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
inst_queue.hh Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
inst_queue_impl.hh Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
isa_specific.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
lsq.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq.hh o3 cpu: remove some unused buggy functions in the lsq 2012-12-06 04:36:51 -06:00
lsq_impl.hh o3 cpu: remove some unused buggy functions in the lsq 2012-12-06 04:36:51 -06:00
lsq_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq_unit.hh o3 cpu: remove some unused buggy functions in the lsq 2012-12-06 04:36:51 -06:00
lsq_unit_impl.hh o3: Fix issue with LLSC ordering and speculation 2013-01-07 13:05:33 -05:00
mem_dep_unit.cc clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
mem_dep_unit.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
mem_dep_unit_impl.hh LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper. 2011-08-19 15:08:07 -05:00
O3Checker.py cpu: Add header files for checker CPUs 2012-11-02 11:32:01 -05:00
O3CPU.py cpu: O3 add a header declaring the DerivO3CPU 2012-11-02 11:32:01 -05:00
regfile.hh Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
rename.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rename.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
rename_impl.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
rename_map.cc o3: missing newlines on some dprintfs 2011-06-10 22:15:32 -04:00
rename_map.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
rob.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rob.hh O3 CPU: Provide the squashing instruction 2012-02-10 08:37:28 -06:00
rob_impl.hh O3 CPU: Provide the squashing instruction 2012-02-10 08:37:28 -06:00
sat_counter.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
sat_counter.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
SConscript cpu: O3 add a header declaring the DerivO3CPU 2012-11-02 11:32:01 -05:00
SConsopts cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
scoreboard.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
scoreboard.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
store_set.cc LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper. 2011-08-19 15:08:07 -05:00
store_set.hh LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper. 2011-08-19 15:08:07 -05:00
thread_context.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
thread_context.hh cpu: rename the misleading inSyscall to noSquashFromTC 2013-01-07 13:05:33 -05:00
thread_context_impl.hh arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
thread_state.hh cpu: rename the misleading inSyscall to noSquashFromTC 2013-01-07 13:05:33 -05:00