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gem5/src/mem
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Brad Beckmann 173a786921 ruby: more flexible ruby tester support 
This patch allows the ruby random tester to use ruby ports that may only
support instr or data requests.  This patch is similar to a previous changeset
(8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets.
This current patch implements the support in a more straight-forward way.
Since retries are now tested when running the ruby random tester, this patch
splits up the retry and drain check behavior so that RubyPort children, such
as the GPUCoalescer, can perform those operations correctly without having to
duplicate code.  Finally, the patch also includes better DPRINTFs for
debugging the tester.
2015-07-20 09:15:18 -05:00
..
cache arm: Add missing explicit overrides for classic caches 2015-11-15 21:28:00 +00:00
probes misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
protocol slicc: fixes for the Address to Addr changeset (11025) 2015-11-13 17:30:58 -05:00
ruby ruby: more flexible ruby tester support 2015-07-20 09:15:18 -05:00
slicc slicc: fixes for the Address to Addr changeset (11025) 2015-11-13 17:30:58 -05:00
abstract_mem.cc mem: Add an option to perform clean writebacks from caches 2015-11-06 03:26:43 -05:00
abstract_mem.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
AbstractMemory.py mem: Change AbstractMemory defaults to match the common case 2013-08-19 03:52:33 -04:00
addr_mapper.cc mem: addr_mapper: restore old address if request not sent 2015-05-30 13:45:17 +02:00
addr_mapper.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
AddrMapper.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
bridge.cc mem: Use the packet delays and do not just zero them out 2015-11-06 03:26:36 -05:00
bridge.hh mem: Align rules for sinking inhibited packets at the slave 2015-11-06 03:26:35 -05:00
Bridge.py mem: Tidy up the bridge with const and additional checks 2013-06-27 05:49:49 -04:00
coherent_xbar.cc mem: Add an option to perform clean writebacks from caches 2015-11-06 03:26:43 -05:00
coherent_xbar.hh mem: Unify delayed packet deletion 2015-11-06 03:26:21 -05:00
comm_monitor.cc mem: Pass snoop retries through the CommMonitor 2015-10-14 13:32:28 -04:00
comm_monitor.hh mem: Pass snoop retries through the CommMonitor 2015-10-14 13:32:28 -04:00
CommMonitor.py mem: Move trace functionality from the CommMonitor to a probe 2015-08-04 10:29:13 +01:00
dram_ctrl.cc mem: Enforce insertion order on the cache response path 2015-11-06 03:26:37 -05:00
dram_ctrl.hh mem: Unify delayed packet deletion 2015-11-06 03:26:21 -05:00
DRAMCtrl.py mem: hmc: minor fixes 2015-11-03 12:17:58 -06:00
drampower.cc mem: Fix search-replace issues in DRAMPower wrapper license 2015-11-25 13:52:56 -05:00
drampower.hh mem: Fix search-replace issues in DRAMPower wrapper license 2015-11-25 13:52:56 -05:00
dramsim2.cc mem: Align rules for sinking inhibited packets at the slave 2015-11-06 03:26:35 -05:00
dramsim2.hh mem: Unify delayed packet deletion 2015-11-06 03:26:21 -05:00
DRAMSim2.py mem: Add a wrapped DRAMSim2 memory controller 2014-02-18 05:50:53 -05:00
dramsim2_wrapper.cc mem: Add a wrapped DRAMSim2 memory controller 2014-02-18 05:50:53 -05:00
dramsim2_wrapper.hh mem: Add a wrapped DRAMSim2 memory controller 2014-02-18 05:50:53 -05:00
external_master.cc mem: Add ExternalMaster and ExternalSlave ports 2014-10-16 05:49:56 -04:00
external_master.hh mem: Add ExternalMaster and ExternalSlave ports 2014-10-16 05:49:56 -04:00
external_slave.cc mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
external_slave.hh mem: Add ExternalMaster and ExternalSlave ports 2014-10-16 05:49:56 -04:00
ExternalMaster.py mem: Add ExternalMaster and ExternalSlave ports 2014-10-16 05:49:56 -04:00
ExternalSlave.py mem: Add ExternalMaster and ExternalSlave ports 2014-10-16 05:49:56 -04:00
fs_translating_port_proxy.cc mem: Use const pointers for port proxy write functions 2014-12-02 06:07:38 -05:00
fs_translating_port_proxy.hh mem: Use const pointers for port proxy write functions 2014-12-02 06:07:38 -05:00
hmc_controller.cc mem: hmc: adds controller 2015-11-03 12:17:56 -06:00
hmc_controller.hh mem: hmc: adds controller 2015-11-03 12:17:56 -06:00
HMCController.py mem: hmc: adds controller 2015-11-03 12:17:56 -06:00
mem_checker.cc mem: Fix initial value problem with MemChecker 2015-02-16 03:34:47 -05:00
mem_checker.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
mem_checker_monitor.cc mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
mem_checker_monitor.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
mem_object.cc Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
mem_object.hh Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
MemChecker.py mem: Add MemChecker and MemCheckerMonitor 2014-12-23 09:31:17 -05:00
MemObject.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
mport.cc MEM: Separate snoops and normal memory requests/responses 2012-04-14 05:45:07 -04:00
mport.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
multi_level_page_table.cc mem: adding a multi-level page table class 2014-04-01 12:18:12 -05:00
multi_level_page_table.hh x86: Add missing explicit overrides for X86 devices 2015-10-23 09:51:12 -04:00
multi_level_page_table_impl.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
noncoherent_xbar.cc sim: Decouple draining from the SimObject hierarchy 2015-07-07 09:51:05 +01:00
noncoherent_xbar.hh sim: Decouple draining from the SimObject hierarchy 2015-07-07 09:51:05 +01:00
packet.cc mem: remove acq/rel cmds from packet and add mem fence req 2015-12-09 22:56:31 -05:00
packet.hh mem: remove acq/rel cmds from packet and add mem fence req 2015-12-09 22:56:31 -05:00
packet_access.hh mem: Cleanup packet accessor methods 2015-08-07 09:59:28 +01:00
packet_queue.cc mem: Order packet queue only on matching addresses 2015-11-06 03:26:38 -05:00
packet_queue.hh mem: Order packet queue only on matching addresses 2015-11-06 03:26:38 -05:00
page_table.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
page_table.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
physical.cc base: Declare a type for context IDs 2015-08-07 09:59:13 +01:00
physical.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
port.cc mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
port.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
port_proxy.cc mem: Clean up Request initialisation 2015-01-22 05:00:53 -05:00
port_proxy.hh mem: Use const pointers for port proxy write functions 2014-12-02 06:07:38 -05:00
qport.hh mem: Enforce insertion order on the cache response path 2015-11-06 03:26:37 -05:00
request.hh cpu: Support virtual addr in elastic traces 2015-12-07 16:42:16 -06:00
SConscript mem: hmc: serial link model 2015-11-03 12:17:57 -06:00
se_translating_port_proxy.cc mem: Use const pointers for port proxy write functions 2014-12-02 06:07:38 -05:00
se_translating_port_proxy.hh mem: Use const pointers for port proxy write functions 2014-12-02 06:07:38 -05:00
serial_link.cc mem: hmc: serial link model 2015-11-03 12:17:57 -06:00
serial_link.hh mem: hmc: serial link model 2015-11-03 12:17:57 -06:00
SerialLink.py mem: hmc: serial link model 2015-11-03 12:17:57 -06:00
simple_mem.cc mem: Use the packet delays and do not just zero them out 2015-11-06 03:26:36 -05:00
simple_mem.hh mem: Use the packet delays and do not just zero them out 2015-11-06 03:26:36 -05:00
SimpleMemory.py mem: Add an internal packet queue in SimpleMemory 2013-08-19 03:52:25 -04:00
snoop_filter.cc mem: Add an option to perform clean writebacks from caches 2015-11-06 03:26:43 -05:00
snoop_filter.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
stack_dist_calc.cc misc: Appease clang static analyzer 2015-11-06 03:26:16 -05:00
stack_dist_calc.hh mem: Redesign the stack distance calculator as a probe 2015-08-04 10:29:13 +01:00
tport.cc mem: Unify delayed packet deletion 2015-11-06 03:26:21 -05:00
tport.hh mem: Unify delayed packet deletion 2015-11-06 03:26:21 -05:00
xbar.cc sim: Refactor and simplify the drain API 2015-07-07 09:51:05 +01:00
xbar.hh mem: hmc: minor fixes 2015-11-03 12:17:58 -06:00
XBar.py mem: Add snoop filters to L2 crossbars, and check size 2015-09-25 07:26:57 -04:00