mem/bus.hh:
Inital crack at a bus object that has ports. Still need to clean up the include file issues.
mem/mem_object.hh:
Decleration of a base memory object. Derives from simobject and adds a function to get the port associated with the object.
mem/packet.hh:
Inital crack at the packet decleration. Still need to clean up the include file issues.
mem/port.hh:
Inital crack at the port decleration. Still need to clean up the include file issues.
mem/request.hh:
Inital crack at the request decleration. Still need to clean up the include file issues.
--HG--
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of tabs so using different editors is consistent
util/emacs/m5-c-style.el:
Default to inserting spaces instead of tabs so using different
editors is consistent
--HG--
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Needed in the interim until we port the old model over
to the new interface. Long term we should have a cleaner
solution for controlling which models get compiled in.
SConscript:
Move old FullCPU source file list to separate full_cpu_sources
list so we can choose to not include it in compile.
arch/isa_parser.py:
Hack to avoid generating FullCPU execute files.
Need a better way to control this.
cpu/exetrace.cc:
Don't include old FullCPU-specific headers (apparently
unnecessary anyway--or if not they should be).
--HG--
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memory model. These changes really should have been part of the
previous changeset.
SConscript:
Move System and PhysicalMemory sources from being full_system_sources
to base_sources, since they are now used in syscall emulation also.
Also add source files for PageTable and ProxyMemory objects.
Actual source files for PhysicalMemory and ProxyMemory are not committed
yet since they still need to be ported from old interface.
--HG--
extra : convert_revision : cb39e3b13d71429b7ee6082794dc09428cde989f
System object now exists for both fullsys and syscall emulation, as the
latter needs it so that Process objects can find the shared PhysicalMemory
for initialization.
Changes are incomplete: still need to fix up Process (& EioProcess) memory
initialization and syscall emulation code for new mem interface.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
cpu/base.cc:
cpu/base.hh:
Take System argument in constructor.
cpu/exec_context.cc:
Take System argument in constructor.
Merge two constructors into a single one.
cpu/exec_context.hh:
Take System argument in constructor.
Merge two constructors into a single one.
Replace dummy translation with lookup in Process object's page table.
python/m5/objects/Process.py:
Add System parameter to Process object (& subobjects).
python/m5/objects/System.py:
Segregate full-system only Process parameters (most of them!).
sim/process.cc:
Take System argument in constructor.
Move initialization to startup() callback to occur after system & cpus
are initialized.
Generate ProxyMemory object to pass to loader for transparent
virtual page allocation.
sim/process.hh:
Take System argument in constructor.
Move initialization to startup() callback to occur after system & cpus
are initialized.
sim/system.cc:
sim/system.hh:
Enable System object for non-full-system too.
Basically involved putting most of the existing code
inside '#ifdef FULL_SYSTEM'.
Key thing needed for syscall emulation at this point is
the PhysicalMemory object (for Process initialization).
--HG--
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All of the code literals are empty as of now. As much as possible instructions were organized into relevant "formats"
and also references to the tables I used from the MIPS manual were noted via appropriate comments.
--HG--
extra : convert_revision : 9b44fb40e900061a4cdb290b6a5aaceb9750ae13
arch/mips/isa_desc/bitfields.h:
Change from table names to actual bitfield name ...
--HG--
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- this will decode the instructions but not doing anything to create the C++ object yet
(the 1st of many steps!)
arch/mips/isa_desc/bitfields.h:
initial bitfield constants ... copied some from original alpha bitfields
arch/mips/isa_desc/decoder.h:
decoder function skeleton pt.1
- this will decode the instructions but not doing anything to create the C++ object yet
(the 1st of many steps!)
--HG--
extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
SConscript:
There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created.
arch/isa_parser.py:
The isa parser now supports include directives. These are done with ##include
build/SConstruct:
The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type.
arch/alpha/SConscript:
This SConscript adds the alpha specific source
arch/sparc/isa_desc/operands.h:
This sets up the operand types that the sparc isa uses
arch/sparc/isa_traits.cc:
Implementation of sparc specific things, like a register file with windows
build/build_options/default/SPARC_SE:
The default options for a sparc syscall emulation build.
--HG--
extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
arch/sparc/isa_desc/bitfields.h:
This file defines the bit fields used by the isa description system
arch/sparc/isa_desc/decoder.h:
This file describes the decoder for the isa description system
arch/sparc/isa_desc/formats.h:
This file declares the instruction formats
arch/sparc/isa_desc/formats/basic.format:
This file implements the "basic" instruction format
arch/sparc/isa_desc/formats/branch.format:
This file implements the "branch" instruction format
arch/sparc/isa_desc/formats/integerop.format:
This file implements the "integerop" instruction format
arch/sparc/isa_desc/formats/mem.format:
This file implements the "mem" instruction format
arch/sparc/isa_desc/formats/noop.format:
This file implements the "noop" instruction format
arch/sparc/isa_desc/formats/trap.format:
This file implements the "trap" instruction format
arch/sparc/isa_desc/includes.h:
This file is all of the inclues that are used by the isa description system
--HG--
extra : convert_revision : 12a2ffe949317b8b57d83263a4261131b9432c2a
needed in a few more cases.
base/intmath.hh:
align arg to roundUp should be int, not template class
sim/process.cc:
sim/syscall_emul.hh:
No need for explicit template arg now that roundUp is fixed.
--HG--
extra : convert_revision : f9f4639e022acb9f427e8d30d81c782504437c53
without using the jobfile.
util/stats/db.py:
util/stats/profile.py:
Make it possible to send job as a string and to set the system
separately from the job.
--HG--
extra : convert_revision : 08aaebd3f9a1643bd41953b43f3b80dc97e6592f
cpu/simple/cpu.cc:
Properly set the Instruction Read bit in the Memory Request
--HG--
extra : convert_revision : e1a4756f32718fd8ef3ac3db16625bd6d8f07cc5
dev/pktfifo.hh:
we can't modify i because it's used further down to remove
the packet from the fifo. Instead, copy the iterator and
modify that to get the previous packet.
dev/sinic.cc:
- don't change the transmit state and kick the machine unless
we're at the head of the txList.
- add a couple of debugging statements to figure out how far
along we've gotten in processing a packet.
- assert that the current tx vnic has something to do when
we start processing the state machine.
--HG--
extra : convert_revision : 588fe2c7d810be0e3d8d39c5cc0ec8a72119517e
from #ifdef DEBUG to #ifndef NDEBUG
base/remote_gdb.cc:
make the remote debugger gdb stuff work in m5.opt
sim/system.cc:
sim/system.hh:
make the console panic break event happen in m5.opt
--HG--
extra : convert_revision : 044a9b7cdacb058112388a31315e45c5d8cf70fd
separate the rx thread and tx thread and get rid of the dedicated flag.
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
python/m5/objects/Ethernet.py:
dedicated flag goes away, we have new individual flags for
rx thread and tx thread
dev/sinic.cc:
Virtualize sinic
- The io registers are replicated many times in memory, allowing the NIC to
differentiate among several virtual interfaces.
- On the TX side, this allows multiple CPUs to initiate transmits at the same
time without locking in the software. If a partial packet is transmitted,
then the state machine blocks waiting for that virtual interface to complete
its packet. Then the state machine will move on to the next virtual
interface. The commands are kept in fifo order.
- On the RX side, multiple partial transmits can be simultaneously done.
Though a packet does not deallocate its fifo space until all preceeding
packets in the fifo are deallocated. To enable multiple receives, it
is necessary for each virtual nic to keep its own information about its
progress through the state machine.
dev/sinic.hh:
Virtualize sinic
Receive state must be virtualized since we allow the receipt of packets in
parallel.
dev/sinicreg.hh:
Virtualize sinic
separate rx thread and tx thread
create a soft interrupt and add a command to trigger it.
pad out the reserved bits in the RxDone and TxDone regs
--HG--
extra : convert_revision : c10bb23a46a89ffd1e08866c1f1621cb98069205
and to remove elements in the middle of the fifo. These elements
do not free space, they are just marked removed. Space is only
freed from the front of the fifo.
dev/etherpkt.cc:
serialize the current slack
dev/etherpkt.hh:
add "slack" to the ethernet packet. It is to be used by any fifo that
the packet is currently in to account for extra space that the packet
may be occupying due to the fifo organization.
--HG--
extra : convert_revision : 8e7c541ba316a9a76495c54cc5f707f8fc65b6d5
options, making existing options more visible and dealing with
holes in data better.
util/stats/barchart.py:
- move the options for BarChart to a base class ChartOptions so
they can be more easily set and copied.
- add an option to set the chart size (so you can adjust the aspect ratio)
- don't do the add_subplot thing, use add_axes directly so we can
affect the size of the figure itself to make room for the legend
- make the initial array bottom floating point so we don't lose precision
- add an option to set the limits on the y axis
- use a figure legend instead of an axes legend so we can put the legend
outside of the actual chart. Also add an option to set the fontsize of
the legend.
- initial hack at outputting csv files
util/stats/db.py:
don't print out an error when the run is missing from the database
just return None, the error will be print elsewhere.
util/stats/output.py:
- make StatOutput derive from ChartOptions so that it's easier to
set default chart options.
- make the various output functions (graph, display, etc.) take the
name of the data as a parameter instead of making it a parameter to
__init__. This allows me to create the StatOutput object with
generic parameters while still being able to specialize the name
after the fact
- add support for graph_group and graph_bars to be applied to multiple
configuration groups. This results in a cross product of the groups
to be generated and used.
- flush the html file output as we go so that we can load the file
while graphs are still being generated.
- make the proxy a parameter to the graph function so the proper system's
data can be graphed
- for any groups or bars that are completely missing, remove them from
the graph. This way, if we decide not to do a set of runs, there won't
be holes in the data.
- output eps and ps by default in addition to the png.
util/stats/profile.py:
- clean up the data structures that are used to store the function
profile information and try our best to avoid keeping extra data
around that isn't used.
- make get() return None if a job is missing so we know it was
missing rather than the all zeroes thing.
- make the function profile categorization stuff total up to 100%
- Fixup the x-axis and y-axis labels.
- fix the dot file output stuff.
util/stats/stats.py:
support the new options stuff for StatOutput
--HG--
extra : convert_revision : fae35df8c57a36257ea93bc3e0a0e617edc46bb7
on the test system.
add an option for pio_delay_write to run.py
util/stats/stats.py:
full0 -> run0 due to run.py change
sim_ticks doesn't make sense with tick = ps, so use
one of the cpu's numCycles paramter
--HG--
extra : convert_revision : db9dbe014549d823edc10395f5241db5e907df01
configs/boot/iscsi-client.rcS:
Clean up the newly updated iscsi-client script.
Reduce the writeback period so writes occur more frequently.
--HG--
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arch/alpha/alpha_linux_process.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi).
--HG--
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output for sinic
dev/sinic.cc:
add the cpu number of the request to various panic and trace
output
--HG--
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dev/ns_gige.cc:
add support for delaying pio writes until the cache access occurs
the only write we delay are for CR_TXE and CR_RXE
dev/sinic.cc:
dev/sinic.hh:
the txPioRequest and rxPioRequest things were more or less bogus
add support for delaying pio writes until the cache access occurs
dev/sinicreg.hh:
Add delay_read and delay_write to the register information struct
for now, we won't delay any reads, and we'll delay the writes that
initiate DMAs
python/m5/objects/Ethernet.py:
add a parameter to delay pio writes until the timing access
actually occurs.
--HG--
extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d
