Commit graph

745 commits

Author SHA1 Message Date
Steve Reinhardt
d53c6c168a Get software prefetching to work in full-system mode.
Mostly a matter of keeping prefetches to invalid addrs
from messing up VM IPRs.  Also discovered that wh64s were
not being treated as prefetches, when they really should be
(for the most part, anyway).

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
    - Add NO_FAULT MemReq flag to indicate references that should not
    cause page faults (i.e., prefetches).
arch/alpha/ev5.cc:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
    - Add Fault trace flag.
arch/alpha/isa_desc:
    - Add NO_FAULT MemReq flag to indicate references that should not
    cause page faults (i.e., prefetches).
    - Mark wh64 as a "data prefetch" instruction so it gets controlled
    properly by the FullCPU data prefetch control switch.
    - Align wh64 EA in decoder so issue stage doesn't need to worry about it.
arch/alpha/isa_traits.hh:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
base/traceflags.py:
    - Add Fault trace flag.
cpu/simple_cpu/simple_cpu.hh:
    - Pass MemReq flags to writeHint() operation.
cpu/static_inst.hh:
    Update comment re: prefetches.

--HG--
extra : convert_revision : 62e466b0f4c0ff9961796270fa2e371ec24bcbb6
2004-06-15 10:48:08 -07:00
Steve Reinhardt
7b24ae00dc Rename '*.odesc' files to '*.od'.
--HG--
extra : convert_revision : 68b4f1cc414ab67e7bd19682854ef3f0b28986c0
2004-06-09 21:01:20 -07:00
Steve Reinhardt
23a6f21ff9 Merge zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
--HG--
extra : convert_revision : 10205d5b7bd10a5894dde9481d0909e909760874
2004-06-09 20:53:29 -07:00
Steve Reinhardt
1c782ad134 Minor restructuring of Python config code, mostly to avoid walking
the source tree for *.odesc files every time we run the script.
This is now factored out into load_odesc.py, which should be used
to generate m5odescs.py, which is then used as the source of object
& parameter definitions.

util/config/m5configbase.py:
    - Move odesc loading code to separate load_odescs.py, so maybe someday
    that can be done once at build time.
    - Print out children of a node in the order they are added.
    - Automatically assign a parent-less node to the first node for which it
    is used as the value of a parameter.  (Easier demonstrated than explained.)
    - Calculate object paths dynamically when requested rather than trying
    to keep them up to date as objects get assigned to parents.

--HG--
rename : util/config/m5config.py => util/config/m5configbase.py
extra : convert_revision : 2183a09d32f3862ab377e0a929715f30505a03cb
2004-06-09 20:46:29 -07:00
Erik Hallnor
7edeb34905 Don't print 0 stats for memory commands we don't see.
--HG--
extra : convert_revision : e72c8bec85c72a48b0b5997d184922faf46c456c
2004-06-09 14:41:06 -04:00
Erik Hallnor
12d1b12043 Make TraceCPU only compile in non-fullsystem.
--HG--
extra : convert_revision : 5df611ae03f41093257672c0ad46bfddc58e515c
2004-06-08 20:11:40 -04:00
Erik Hallnor
e7c7c92184 Tracing now works for upto 4 threads. Easy change to get it to work for more, but I don't have any test handy to test it.
cpu/trace/reader/m5_reader.cc:
    Add thread num.
cpu/trace/trace_cpu.cc:
    Increase thread count to 4, might want to make this a parameter (but it only really costs us storage).

--HG--
extra : convert_revision : 97cd7843668a3ef85aad06e3180dc04d2ca30ac1
2004-06-08 19:52:49 -04:00
Erik Hallnor
5f4297e865 Add the capability to read and write memory trace files. Currently is cycle accurate for a single thread FullCPU.
--HG--
extra : convert_revision : f8fe545313eb307cc6f5ff2c23894cc9870b1d5b
2004-06-08 17:31:04 -04:00
Steve Reinhardt
73308846cc Rename OpClass enum in .odesc file too.
--HG--
extra : convert_revision : cb1824a1b6747fabf44ffcf40b45b71b052b2253
2004-05-31 17:39:06 -07:00
Steve Reinhardt
53dde8579b Renamed OpClass enum members: they all end in 'Op' now.
Got rid of two inconsistent sets of strings that corresponded
to this enum, and replaced with a single set that clearly
matches the enum names.

arch/alpha/isa_desc:
arch/isa_parser.py:
cpu/full_cpu/op_class.hh:
    Renamed OpClass enum members.

--HG--
extra : convert_revision : bf596f7568a20b2e77c07ac349f253135141aef4
2004-05-31 16:19:31 -07:00
Steve Reinhardt
a95edd1e45 Ignore fast_cpu_exec.cc.
--HG--
extra : convert_revision : 31495fbb3568a09e763978ea59e36cb239090fda
2004-05-31 15:22:22 -07:00
Steve Reinhardt
7b400262c5 Add parameter defaults to .odesc files. There was a bug in
extract_odesc.py that caused these to get left out.

--HG--
extra : convert_revision : 32e76c8e699f3dd72937e92217f3ab43fb53b4de
2004-05-31 15:21:14 -07:00
Kevin Lim
6964ecd1cf Updated FastCPU model with all the recent changes.
arch/alpha/ev5.cc:
    Updated to support new forms of setIntReg and setFloatRegDouble.  Will need to be cleaned up in the future.
arch/isa_parser.py:
    Added in FastCPU model.

--HG--
extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
2004-05-28 14:42:59 -04:00
Kevin Lim
67b5f6afc1 Merged in new FastCPU stuff with existing code.
arch/alpha/ev5.cc:
    Added templatized processInterrupts() function that can be used by all of the CPU models.
arch/alpha/isa_desc:
    Merged in changes to remove CPU dependence.
arch/isa_parser.py:
    Merged in changes.
cpu/static_inst.hh:
    Includes FastCPU execute methods.

--HG--
extra : convert_revision : fcaa1dca35a9b316c73982bec8680df564f50bd8
2004-05-28 11:41:52 -04:00
Kevin Lim
a896960cbf FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking.
Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile.

arch/alpha/alpha_memory.cc:
    The regfile has been changed so it no longer has the opcode and ra.  Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
    Moved code that once existed within simpleCPU to ev5, and templatized it.
    This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
    Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
    Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
    Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
    Removed opcode and ra from the regfile.  The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
    Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
    Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
    Added in a more generic trap function so "ev5_trap" doesn't need to be called.  It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
    Exec context now has the instruction within it.  Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
    Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
    Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
    Added declaration for execute() using FastCPUExecContext.

--HG--
extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
2004-05-27 17:46:16 -04:00
Ali Saidi
4f34dda81c test to see if pushing to m5-tru64 triggers an e-mail
--HG--
extra : convert_revision : df7aab669a8521d031c7202e36c3c086fa979854
2004-05-27 14:20:50 -04:00
Steve Reinhardt
12c6bef21a postint, postext:
Fix output path /m5 -> /z/m5

--HG--
extra : convert_revision : 11ebcc7e62f02be8b0aeb8857eebc33a27e29513
2004-05-27 14:12:49 -04:00
Steve Reinhardt
1c1acf553a Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5

--HG--
extra : convert_revision : 38d50d3d3640f02622e5ace5ac12b67d63eda3f0
2004-05-27 14:06:39 -04:00
Steve Reinhardt
c5c4533596 config_files.doxygen:
Apparently <> don't need backslashes if they're inside dbl-quoted strings.

--HG--
extra : convert_revision : dd5294781d0ef818d1a5b622f3415510baefb402
2004-05-27 14:06:29 -04:00
Nathan Binkert
3a0dfc43d1 make the interaction of the stats event stuff with the
database work better.

base/stats/events.cc:
    properly connect to the database
base/stats/mysql.cc:
    cleanup the event stuff too

--HG--
extra : convert_revision : f05fd6456decc9c4f95beff5c12497439e45f886
2004-05-23 12:53:34 -04:00
Nathan Binkert
6cf04bf31e fix column name for indexes
--HG--
extra : convert_revision : 34831eed6b218e470096f010438fd2f32a4960c5
2004-05-21 15:06:04 -04:00
Nathan Binkert
f622d74f81 add a few statistics events
arch/alpha/ev5.cc:
    Add an event for faults
cpu/simple_cpu/simple_cpu.cc:
    add events for uncached reads/writes

--HG--
extra : convert_revision : 747bdf12761e2de6ebbf54fecc9e0b71915b3a02
2004-05-21 13:58:39 -04:00
Nathan Binkert
fee1e1ec0a Add support for event tracking. Esentially this puts a sequence
of events into the database for a given run.

base/stats/mysql.cc:
base/stats/mysql.hh:
    reorganize mysql stat stuff so that other stuff can use
    the same database connection
base/traceflags.py:
    Trace flag to print out events

--HG--
extra : convert_revision : 4d502532ed0ba40b42baefee46b2c99defcc620c
2004-05-21 13:57:44 -04:00
Nathan Binkert
b4405682d9 Change the namespace Statistics to Stats
--HG--
extra : convert_revision : 3084b292bbe2e8a392af8e99a31763ca0b0a9467
2004-05-21 13:03:17 -04:00
Erik Hallnor
47604c8c89 Update the adaptive cache compression scheme.
--HG--
extra : convert_revision : 50c158b0545c29c03e346f1bd2952951ac77659b
2004-05-20 23:26:44 -04:00
Nathan Binkert
2674b6920f Merge zizzer.eecs.umich.edu:/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/ziff/z/binkertn/research/m5/latest

--HG--
extra : convert_revision : d5f03880c6564b80f662a467524c79aa90b1a0b0
2004-05-19 22:00:30 -04:00
Nathan Binkert
2cf71ff6ef Replaced by python
--HG--
extra : convert_revision : 5c95c2b3169b8b1a51166d7f8fcde3de39fa30f9
2004-05-19 21:54:05 -04:00
Steve Reinhardt
27a6e8258d Add a level of indirection to the register accessors used in
instruction execute methods.  Register i now means the instruction's
i'th src (or dest) operand, not architectural register i.  Current
models that use the architectural reg index can look that up easily
in the instruction object.  Future models that do register renaming
should find this much simpler to deal with.

arch/isa_parser.py:
    Generate register accessors with an extra level of indirection.
cpu/simple_cpu/simple_cpu.hh:
    Modify register accessors to use an extra level of indirection.

--HG--
extra : convert_revision : f4c7d6bfa92fb2ea6251f31ee368809c3643f08f
2004-05-18 22:09:13 -07:00
Steve Reinhardt
4c55d26e66 Replace explicit xc->misspeculating() tests in execute() methods
with an IsNonSpeculative flag.
No effect on results of non-full-system or SimpleCPU.
Very small impact on full-system FullCPU runs since old wrong-path
call_pal insts used to change the PC, where now they're treated
as no-ops.

arch/alpha/isa_desc:
    Get rid of xc->misspeculating() checks, use IsNonSpeculative flag instead.
cpu/static_inst.hh:
    Add IsNonSpeculative flag and isNonSpeculative() method to test it.

--HG--
extra : convert_revision : 7ec536bfc28b905c429c09eb920ed73ef2beeeba
2004-05-18 16:09:02 -07:00
Steve Reinhardt
02af86f7e8 Merge zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
--HG--
extra : convert_revision : 4dae71fe3482737a22745b27c2ca6983191c4a18
2004-05-17 12:10:28 -07:00
Lisa Hsu
b8082eb508 lift system-independent binning stuff out of Tru64System into System.
kern/tru64/tru64_system.cc:
    make binned_fns a parameter for System in addition to Tru64System.  Do all the fnEvents setting at the System level, since that is system-independent.
kern/tru64/tru64_system.hh:
    deal with FnEvents in the System, and move some fns over to System.
sim/system.cc:
sim/system.hh:
    lift binning stuff into System out of Tru64System

--HG--
extra : convert_revision : 591dee6f2013f5c43037726c529a00682b5cf82e
2004-05-17 15:08:24 -04:00
Steve Reinhardt
9ca875f189 Merge zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
--HG--
extra : convert_revision : 266d03e82a04cca07f669f778ad11907f2f003d2
2004-05-17 11:50:02 -07:00
Steve Reinhardt
1d545281b9 Significant changes to ISA description to completely factor
out CPU model.  ISA description now generates multiple
output source files to (in theory) reduce compilation time.

arch/alpha/isa_desc:
    Update for parser changes.  Move most constructors
    out of class declarations (which are now in decoder.hh)
    and into decoder.cc.  Move all execute() methods into
    exec output.
arch/isa_parser.py:
    Significant changes to make ISA description completely
    independent of CPU model, and isolate model-dependent parts
    of parser into one little class (CpuModel).  Also split up code
    output into multiple files (a header, a main source file, and
    per-cpu execute() method files).

    Noticeable changes to language as a result.  See updated Doxygen
    documentation.
cpu/simple_cpu/simple_cpu.hh:
    SimpleCPUExecContext typedef no longer needed.
    Add forward declaration of Process.
cpu/static_inst.hh:
    SimpleCPUExecContext and FullCPUExecContext typedefs no longer needed.
    Make eaCompInst() and memAccInst() return const refs.

--HG--
extra : convert_revision : 71471f267804fafd0a881bac7445677e76334daf
2004-05-17 11:49:46 -07:00
Lisa Hsu
73501ea38f push the new system_events file that i was prevented from pushing way back when cable died. :(. also, fix the printing of binned stats, it was printing hex values instead of bin names.
base/stats/text.cc:
    fix the printing of binned stats.

--HG--
extra : convert_revision : 3a04d004f5ea1d90536f7102fce946fd6dd34613
2004-05-17 13:22:19 -04:00
Lisa Hsu
5d959ce32e Merge zizzer.eecs.umich.edu:/bk/m5
into shizzle.(none):/home/hsul/work/m5

--HG--
extra : convert_revision : fb775c1ed5ac9712929bbd7186b9ab13e90e2dc1
2004-05-17 10:40:45 -04:00
Nathan Binkert
32a8827b3e Now that the generation stuff is working, make the gendir
work correctly.

--HG--
extra : convert_revision : 08a5147f5a5cac46800eeef47b4a23451a1139c2
2004-05-16 11:41:41 -04:00
Nathan Binkert
c6c7e24145 Make the build process deal with the target arch directory
and generated files a bit better.

--HG--
extra : convert_revision : e2216289bb53fd231e228c2d9d740317c00991bb
2004-05-16 09:28:06 -04:00
Lisa Hsu
9aeea1cfbd Merge zizzer.eecs.umich.edu:/bk/m5
into shizzle.(none):/home/hsul/work/m5

--HG--
extra : convert_revision : e47c4db52bdf074b596591f145ffb1a6443d63a4
2004-05-13 11:40:22 -04:00
Lisa Hsu
7f28ae6b01 lift some things out of the tru64 directory into common directory so linux can use it without replication later.
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
    lift out SkipFuncEvent and FnEvents since these can be used by any OS.
kern/tru64/tru64_system.cc:
    add system_events (the common OS events file)

--HG--
extra : convert_revision : 4d7a843d67459af4d77e433ae3c1b0fbc5f0b56b
2004-05-13 11:40:07 -04:00
Nathan Binkert
f13926c099 Add VPtr class that makes it possible to esentially create
a pointer to an object that lives inside simulated memory.
Useful for doing a bit of analysis of what's going on in
the running kernel.

--HG--
extra : convert_revision : d78089cce5ec4334483a710ba512eaf18d9b0319
2004-05-13 08:08:42 -04:00
Nathan Binkert
2d8777a79b remove the annotation junk
arch/alpha/isa_desc:
    remove the annotation junk
    Move some code to AlphaPseudo where it belongs
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
    remove the annotation junk
    add pseudo instruction code that was previously misplaced

--HG--
extra : convert_revision : 97db8402aa34e0bdf044b138c52331fc9e714986
2004-05-13 08:03:36 -04:00
Nathan Binkert
8bc3ce93cb pass the address of both the old an new pcbb on context
switches.  (Makes other uncommitted code easier to merge.)

arch/alpha/ev5.cc:
    pass the address of both the old an new pcbb on context
    switches

--HG--
extra : convert_revision : bff8c8d1b532ad5f9af6270169bbfb1b5c05256a
2004-05-13 07:28:54 -04:00
Nathan Binkert
6a26c92d6f wrap mbuf stuff in the tru64 namespace since other OSes
may be different

--HG--
extra : convert_revision : 75ea218b5219c7a2b5bf7dca7c52dfff22740478
2004-05-13 07:00:31 -04:00
Nathan Binkert
ce697a592e Avoid sending a signal to ourselves if we're not debugging
--HG--
extra : convert_revision : d6ba1ce30bad4a44d716238a8107c3bff0ce89c4
2004-05-13 06:59:05 -04:00
Nathan Binkert
a4d7bb113a Make a new stat type of Value which is a scalar stat that
proxies for a real C/C++ scalar value or scalar functor.
This replaces the scalar() and functor() terms that were
previously used in formulas.  This helps when dumping
statistics because the formulas are not supposed to change.

cpu/base_cpu.cc:
    Add a number of cycles stat to the cpu object that tracks the
    number of cycles that the cpu has executed.  This starts to pave
    the way for cpu cycles being different from event ticks.
cpu/base_cpu.hh:
    provide a functor for calculating all simulated instructions
    of all CPUs and a virtual function for determining that number.
    To deal with the change from functor() to Value::functor()
cpu/simple_cpu/simple_cpu.cc:
    simTicks -> numCycles
    numInsts is now a real Scalar stat, not a Formula
cpu/simple_cpu/simple_cpu.hh:
    numInsts is now a real Scalar stat, not a Formula
    count all instructions
sim/stat_control.cc:
    simInsts, simTicks, hostMemory, and hostSeconds are no
    longer Statistics::Formula but rather Statistics::Value
    add new stat for tick frequency
sim/stats.hh:
    don't need everything to be extern.
test/Makefile:
    Make stuff work a tad bit better
test/stattest.cc:
    test out Statistics::Value

--HG--
extra : convert_revision : c812e8baa2b17c08abf3a68ed1e1125dc6f2cfb4
2004-05-12 15:49:01 -04:00
Steve Reinhardt
2cc4fd87eb dma_bus_interface_impl.hh:
Fix template param (breaks on g++ 3.3).

--HG--
extra : convert_revision : b469aa9aab105bbc5a72a20a48a4abd2e218ff8c
2004-05-10 22:21:04 -04:00
Steve Reinhardt
7cab07268f Do a better job of factoring out CPU model in ISA description.
(Still not perfect though.)

arch/alpha/isa_desc:
    Do a better job of factoring out CPU model.  (Still not perfect though.)
    Pull execute() methods out of class declarations into separate section
    of file, allowing (1) easier replication for different CPU models and
    (2) a path to putting them all in a separate file.  Force all instruction
    execution context into a single model-dependent class (SimpleCPU itself
    for SimpleCPU, DynInst for FullCPU).
arch/isa_parser.py:
    Do a better job of factoring out CPU model.  (Still not perfect though.)
    Pull execute() methods out of class declarations into separate section
    of file, allowing (1) easier replication for different CPU models and
    (2) a path to putting them all in a separate file.
    Also restructure top level to allow parser to run under interactive
    interpreter session for easier debugging.
cpu/exec_context.hh:
    Add a few new methods to clean up isa_desc.
cpu/simple_cpu/simple_cpu.cc:
cpu/static_inst.hh:
    StaticInst::execute no longer takes a CPU and an ExecContext,
    just a unified FooCPUExecContext.
cpu/simple_cpu/simple_cpu.hh:
    Add methods to redirect calls to ExecContext so SimpleCPU
    can act as sole instruction execution context for itself.
    Typedef SimpleCPU to SimpleCPUExecContext.

--HG--
extra : convert_revision : ecc445503bc585585da5663fe61796580e744da6
2004-05-10 16:10:47 -07:00
Steve Reinhardt
d66ae60f6b Very minor fixes.
util/tracediff:
    stats:file option is now stats:text_file

--HG--
extra : convert_revision : 74b6294da0003345e84bc1533d536dab271b6033
2004-05-08 23:32:30 -07:00
Steve Reinhardt
5685020c82 Merge
--HG--
extra : convert_revision : 7999c243a80482b9feffdf8f3dd4ff061b189377
2004-05-07 19:20:30 -07:00
Nathan Binkert
1d44903071 don't do dependencies on make generate
--HG--
extra : convert_revision : 0dac37a1676e795bf2ebf9572e37b6b78af7929a
2004-05-06 19:01:16 -04:00