dev/pktfifo.cc:
add support for copying arbitrary data out of a
packet fifo
dev/pktfifo.hh:
add support for copying arbitrary data out of a
packet fifo.
Add functions to determine where in the fifo a
particular packet is
--HG--
extra : convert_revision : f8ddc994ce8577f29af0de3fa418a01e4e2cb0f1
util/stats/barchart.py:
clean up some of lisa's messy code
remove trailing whitespace while I'm at it.
--HG--
extra : convert_revision : f2fe6777fb4b458fa1d5b5b743f6274014c229ad
util/stats/chart.py:
add a bool config option for determining
if the legend is inside or outside the figure
--HG--
extra : convert_revision : e862d1832a0cc3c1837758cc247bc77c0a02ec12
util/stats/barchart.py:
Add support for error bars
util/stats/barchart.py:
add support to choose between a legend inside or
outside the figure.
--HG--
extra : convert_revision : 14273e385c106bf27a2013991f9f34ca6551b96c
util/stats/barchart.py:
If there are fewer than 5 colors, pick from a subset of
5 so there is more consistency in colors between graphs
--HG--
extra : convert_revision : 6cf64c2f8ed81e714e24a3ebe5a7a60ca168b231
CPU_MODELS parameter changes.
arch/SConscript:
Fix typo in comment.
cpu/SConscript:
Convert exec signature generator to Action so we can add dependency
on CPU_MODELS environment var.
Print nicer string while we're at it.
Also add some comments.
--HG--
extra : convert_revision : bcb38a7941943cf071dac34cdbb2ece5456b8620
2) make subticks vertical so they can be longer
3) make inner and outer axes farther apart to make room for subtick's vertical labels
--HG--
extra : convert_revision : 91a1aab3f1078921edd53428e6712744210c9f1b
CPU_MODELS parameter. For example:
scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug
Unfortunately the option is not sticky due to a scons
bug with saving & restoring ListOption parameters.
SConscript:
Separate out cpu-model-specific files so they can be conditionally
included based on value of new CPU_MODELS parameter.
Most of these are now handled in cpu/SConscript, except for FullCPU
which is still in this file.
arch/SConscript:
The set of CPU-model-specific execute files must now be
determined from the CPU_MODELS parameter, via the new
cpu_models.py file.
Also pass the list of configured CPU models to isa_parser.py.
arch/isa_parser.py:
Move CpuModel definition and objects out to a
separate file so they can be shared with scons.
Global list of CPU models to generate code for is now
controlled by command-line parameters (so we can do
only a subset of the available ones).
build/SConstruct:
Define new CPU_MODELS ListOption.
cpu/static_inst.hh:
Rename static_inst_impl.hh to static_inst_exec_sigs.hh.
--HG--
extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
into zeep.eecs.umich.edu:/z/saidi/work/m5.head
cpu/simple/cpu.cc:
remove initCPU from constructor
dev/alpha_console.cc:
we are panicing, so no need to return a fault
--HG--
extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9
Now allocate an array of stacks indexed by cpu number which specify
cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for
their stacks before continuing. This change *REQUIRES* a the new
console code to operate correctly.
arch/alpha/ev5.cc:
Add cpuId to initCPU/initIPR functions
cpu/o3/cpu.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Move the cpu initilization into an init() function since it now needs
the CPU id which isn't known at construction
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
instead of the bootstrap variables, add space for 64 cpu stacks in the
alpha access structure.
sim/system.cc:
start all cpus immediately rather than just the first one
--HG--
extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b
Start using SCons File objects to avoid fixed paths in
subordinate SConscripts.
SConscript:
Push isa_parser stuff (including .isa scanner) down into
arch/SConscript.
arch/SConscript:
Create a Builder object for .isa files, including existing scanner.
Return file objects generated by isa-specific SConscript
back up to parent.
arch/alpha/SConscript:
arch/mips/SConscript:
arch/sparc/SConscript:
Convert sources to scons File objects, so file names can be specified
relative to the current directory.
Invoke new builder for isa description, and get generated sources from
there (instead of listing them explicitly).
arch/isa_parser.py:
Get rid of third argument ("include_path").
It was a pain to generate this from scons, and it turned out
it's not needed anyway, since the only included file
(decoder.hh) will be in the same directory as the sources.
--HG--
extra : convert_revision : 36861bcef36763f229704d8cb7a642b4486a3581
SConscript:
Include new arch/SConscript file.
arch/isa_specific.hh:
Get rid of unnecessary ISA_INCLUDE() macro and other
things that were used only for that purpose.
build/SConstruct:
Move list of ISAs to env var ALL_ISA_LIST.
--HG--
extra : convert_revision : 612c7ee4279d57209662be88dc577d80fdbd692c
Now that we have decoder.do, add new files so we can start compiling other files
needed for MIPS syscall emulation mode
arch/mips/linux_process.cc:
arch/mips/linux_process.hh:
New MIPS-specific file
--HG--
rename : arch/alpha/linux_process.cc => arch/alpha/alpha_linux_process.cc
rename : arch/alpha/linux_process.hh => arch/alpha/alpha_linux_process.hh
rename : arch/alpha/tru64_process.cc => arch/alpha/alpha_tru64_process.cc
rename : arch/alpha/tru64_process.hh => arch/alpha/alpha_tru64_process.hh
extra : convert_revision : 2bfc27e8772523cbeb95f40684f9a32fe5554f87
-----
uncomment out detailed model ... just commented to supress some compile errors
arch/isa_parser.py:
uncomment out detailed model ... just commented to supress some compile errors
--HG--
extra : convert_revision : e884b9bd47794409f74043ad1aca6dadd1323185
dev/sinic.cc:
When DPRINTF disappears, reg32 becomes an unused variable. With -Werror, this causes the compile to fail.
--HG--
extra : convert_revision : c003c714228491e060155070d192521c53d9e929
until the cache access occurs. The fundamental problem
is that a subsequent read that occurs functionally will
get a functionally incorrect result that can break
driver code.
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
get rid of pio_delay write and the associated code to move
the write to the cache access function
dev/sinicreg.hh:
no more write delays
python/m5/objects/Ethernet.py:
get rid of pio_delay write
--HG--
extra : convert_revision : 1dcb51b8f4514e717bc334a782dfdf06d29ae69d
and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.
arch/mips/isa/bitfields.isa:
comment change
arch/mips/isa/decoder.isa:
re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
Define LoadMemory & Store Memory formats
Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
change shw->sh and uhw->uh
--HG--
extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
Redo format for Branches and Jumps ( Must update NNPC not NPC )
Now all branches and jumps look like they auto-generate correctly from isa_parser.py!!!
arch/mips/isa/decoder.isa:
Support for All Jump Instructions ..
arch/mips/isa/formats/branch.isa:
Redo format for Branches and Jumps ( Must update NNPC not NPC )
arch/mips/isa/formats/util.isa:
define clear_exe_inst_hazards for later use
--HG--
extra : convert_revision : 63618ed12ee6ed94c47d29619cc1cab2cbaf5cda
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
arch/alpha/faults.hh:
ur
Using cleaned up fault class deiffinitions
--HG--
extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
cpu/base.hh:
cpu/static_inst.hh:
Changed include of targetarch/isa_traits.hh back to arch/isa_traits.hh
cpu/exec_context.hh:
Changed Fault back to Fault *
--HG--
extra : convert_revision : 410f2e2472f8aa5bf92619a5defdf85f689a5597
