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Author SHA1 Message Date
Gabe Black
aa8c6e9c95 CPU: Add readBytes and writeBytes functions to the exec contexts. 2010-08-13 06:16:02 -07:00
Gabe Black
65dbcc6ea1 InOrder: Clean up some DPRINTFs that print data sent to/from the cache. 2010-08-13 06:16:00 -07:00
Gabe Black
52a90a5998 CPU: Tidy up endianness handling for mmapped "IPR"s. 2010-08-13 06:10:45 -07:00
Joel Hestness
73d9a51835 util/m5/m5.c: ensure readfile() buffer pages are in page table 
(and marked dirty, in case that matters) by touching them beforehand
 2010-08-12 17:16:04 -07:00
Joel Hestness
53c241fc16 TimingSimpleCPU: fix NO_ACCESS memory op handling 
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op
doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs
to handle the case where the current status of the CPU is Running
and not DcacheWaitResponse or DTBWaitResponse
 2010-08-12 17:16:02 -07:00
Nathan Binkert
2e9e75447a None, not none 2010-08-08 22:57:16 -07:00
Steve Reinhardt
545a6fcd04 .hgignore: added src/doxygen 2010-07-27 20:00:38 -07:00
Ali Saidi
1b73376b0b ARM: Add regression tests 2010-07-27 01:03:44 -04:00
Timothy M. Jones
97d245278d Power: The condition register should be set or cleared upon a system call 
return to indicate success or failure.
 2010-07-22 18:54:37 +01:00
Timothy M. Jones
607f519800 LSQ Unit: After deleting part of a split request, set it to NULL so that it 
isn't accidentally deleted again later (causing a segmentation fault).
 2010-07-22 18:54:37 +01:00
Timothy M. Jones
28a5ea3f99 Port: Only indicate that a SimpleTimingPort is drained if its send event is 
not scheduled, as well as the transmit list being empty.
 2010-07-22 18:54:37 +01:00
Timothy M. Jones
e50a880297 O3CPU: Fix a bug where stores in the cpu where never marked as split. 2010-07-22 18:52:02 +01:00
Timothy M. Jones
0d301ca4c4 Syscall: Don't close the simulator's standard file descriptors. 2010-07-22 18:47:52 +01:00
Timothy M. Jones
9a3533ec84 O3CPU: O3's tick event gets squashed when it is switched out. When repeatedly 
switching between O3 and another CPU, O3's tick event might still be scheduled
in the event queue (as squashed).  Therefore, check for a squashed tick event
as well as a non-scheduled event when taking over from another CPU and deal
with it accordingly.
 2010-07-22 18:47:43 +01:00
Timothy M. Jones
8c76715979 Power: Provide a utility function to copy registers from one thread context 
to another in the Power ISA.
 2010-07-22 18:47:03 +01:00
Nathan Binkert
21bf6ff101 stats: unify the two stats distribution type better 2010-07-21 18:54:53 -07:00
Nathan Binkert
2a1309f213 stats: cleanup a few small problems in stats 2010-07-21 15:53:53 -07:00
Nathan Binkert
76c92c3e30 python: add a sorted dictionary class 
It would be nice if python had a tree class that would do this for real,
but since we don't, we'll just keep a sorted list of keys and update
it on demand.
 2010-07-21 15:53:53 -07:00
Nathan Binkert
3518416917 python: Add mechanism to override code compiled into the exectuable 
If the user sets the environment variable M5_OVERRIDE_PY_SOURCE to
True, then imports that would normally find python code compiled into
the executable will instead first check in the absolute location where
the code was found during the build of the executable.  This only
works for files in the src (or extras) directories, not automatically
generated files.

This is a developer feature!
 2010-07-21 15:53:52 -07:00
Tushar Krishna
11bb678a80 Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses 2010-07-21 09:55:57 -07:00
Steve Reinhardt
262b2e2b94 SimObject: transparently forward Python attribute refs to C++. 
This tidbit was pulled from a larger patch for Tim's sake, so
the comment reflects functions that haven't been exported yet.
I hope to commit them soon so it didn't seem worth cleaning up.
 2010-07-17 08:56:49 -07:00
Gabe Black
8cec870568 ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault. 2010-07-15 02:11:56 -07:00
Gabe Black
4e3183cb1e ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index. 2010-07-13 22:41:47 -07:00
Steve Reinhardt
897247d63b cache: fix bug in SC upgrade handling 
This bug was introduced with the recent rework of SC
failure handling in cset f97b62be544f.
 2010-07-08 17:56:13 -07:00
Brad Beckmann
a03c1cd6e0 garnet: Added topology print function to Garnet printStats 2010-07-08 16:18:20 -07:00
Tushar Krishna
2f2962fee3 NetworkMessage copy constructor fix 2010-07-08 16:18:20 -07:00
Steve Reinhardt
26f5a9c2cb checkpointing: another small overload fix 
On Nate's advice, overload 'char' as well as 'signed char'
and 'unsigned char'.
 2010-07-05 22:57:23 -07:00
Steve Reinhardt
387cbffb7a sim: allow SimObject subclasses to define classmethods 
(without requiring a leading underscore)
Also a little cleanup on type names in SimObject.py.
 2010-07-05 21:39:38 -07:00
Steve Reinhardt
30ce620d1d sim: fold StartupCallback into SimObject 
There used to be a reason to have StartupCallback
be a separate object, but not any more.  Now
it's just confusing.
 2010-07-05 21:39:38 -07:00
Steve Reinhardt
345dfd1b41 checkpointing: minor cleanup. 
Move some static checkpoint stuff into the
Checkpoint object namespace.
 2010-07-05 21:39:38 -07:00
Steve Reinhardt
820bb3044d checkpointing: fix minor bug 
Somehow we now need to explicitly specialize on
'signed char' and not just 'char' to catch cases
like int8_t
 2010-07-05 21:39:38 -07:00
Steve Reinhardt
cbd65e95db util: add a script for testing checkpointing 
See comments in util/checkpoint-tester.py for details.
 2010-07-05 21:39:38 -07:00
Steve Reinhardt
f98cce5771 process: get rid of some unused code & vars 2010-07-05 21:39:38 -07:00
Steve Reinhardt
2c2f956060 process: minor format/style cleanup 2010-07-05 21:39:38 -07:00
Tushar Krishna
66f0d26059 style: updated garnet to match M5 coding style 2010-06-22 15:36:07 -07:00
Korey Sewell
84489c5874 inorder: remove another debug stat 2010-06-28 07:33:33 -04:00
Korey Sewell
792c18a1fc inorder: remove debugging stat 
m5 doesnt do stats specific to binary and this resource request stat is probably only
useful for people who really know the ins/outs of the model anyway
 2010-06-26 09:41:39 -04:00
Korey Sewell
f2eba81f50 inorder: update regressions from RAS fix 2010-06-25 17:42:55 -04:00
Korey Sewell
868181f24d inorder: Return Address Stack bug 
the nextPC was getting sent to the branch predictor not the current PC, so
the RAS was returning the wrong PC and mispredicting everything.
 2010-06-25 17:42:35 -04:00
Korey Sewell
6bfd766f2c inorder: resource scheduling backend 
replace priority queue with vector of lists(1 list per stage) and place inside a class
so that we have more control of when an instruction uses a particular schedule entry
...
also, this is the 1st step toward making the InOrderCPU fully parameterizable. See the
wiki for details on this process
 2010-06-25 17:42:34 -04:00
Gabe Black
6697d41693 X86: Fix div2 flag calculation. 2010-06-25 00:21:48 -07:00
Korey Sewell
0135cdab8d inorder: update regressions 2010-06-24 15:34:21 -04:00
Korey Sewell
71b67d408b inorder: cleanup virtual functions 
remove the annotation 'virtual' from  function declaration that isnt being derived from
 2010-06-24 15:34:19 -04:00
Korey Sewell
f95430d97e inorder: enforce 78-character rule 2010-06-24 15:34:12 -04:00
Korey Sewell
ecba3074c2 inorder: exe_unit_stats for resolved branches 2010-06-24 13:58:27 -04:00
Korey Sewell
1a73764403 inorder: squash from memory stall 
this applies to multithreading models which would like to squash a thread on memory stall
 2010-06-23 22:09:49 -04:00
Korey Sewell
e17c41c176 inorder: update regressions 2010-06-23 18:21:44 -04:00
Korey Sewell
1f778b3583 inorder: record load/store trace data 2010-06-23 18:21:12 -04:00
Korey Sewell
defab3ffd5 inorder: update branch predictor 
- use InOrderBPred instead of Resource for DPRINTFs
- account for DELAY SLOT in updating RAS and in squashing
- don't let squashed instructions update the predictor
- the BTB needs to use the ASID not the TID to work for multithreaded programs
- add stats for BTB hits
 2010-06-23 18:19:18 -04:00
Korey Sewell
9f0d8f252c inorder-stats: add instruction type stats 
also, remove inst-req stats as default.good for debugging
but in terms of pure processor stats they aren't useful
 2010-06-23 18:18:20 -04:00