Commit graph

4049 commits

Author SHA1 Message Date
Gabe Black
b642ad00eb Implement a stub nnpc for alpha that is read only as npc+4.
--HG--
extra : convert_revision : d08b740d32757fa5471c9bcde9084d59a1d8102d
2006-12-28 14:27:45 -05:00
Gabe Black
9ca6efdb60 Fixed NumMiscArchRegs. This is still a magic number, and it should be set automatically by the miscreg enum. I need to figure out how to do that without including the whole miscregfile.hh and making header spaghetti.
--HG--
extra : convert_revision : eb640c9ef10a188b96f6a079f91abc8f67b9d38c
2006-12-28 14:23:30 -05:00
Ali Saidi
b48a8fb347 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : afd4266bd494bb8f127c06985f343219ded4f637
2006-12-27 14:38:22 -05:00
Ali Saidi
ba14d6d0e1 Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48

src/arch/sparc/tlb.cc:
    Bug fixes in the TLB
    Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
    Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
    itb should be 64 entries too

--HG--
extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
2006-12-27 14:38:07 -05:00
Ali Saidi
ff88f3b13a Compare legion and m5 tlbs for differences
Only print faults instructions that aren't traps or faulting loads

src/cpu/exetrace.cc:
    Compare the legion and m5 tlbs and printout any differences
    Only show differences if the instruction isn't a trap and isn't a memory
    operation that changes the trap level (a fault)
src/cpu/m5legion_interface.h:
    update the m5<->legion interface to add tlb data

--HG--
extra : convert_revision : 6963b64ca1012604e6b1d3c5e0e5f5282fd0164e
2006-12-27 14:35:23 -05:00
Ali Saidi
b6dc902f6a Change MemoryAccess dprintfs to print the data as well
--HG--
extra : convert_revision : 51336fffa5e51a810ad2f6eb29b91c1bfd67824b
2006-12-27 14:32:26 -05:00
Nathan Binkert
9e90bfafb5 No need to use NULL, just use 0
The result of operator= cannot be an l-value

--HG--
extra : convert_revision : df97a57f466e3498bd5a29638cb9912c7f3e1bd4
2006-12-27 10:52:25 -08:00
Kevin Lim
0bd7518480 Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.
--HG--
extra : convert_revision : 5c334ec806305451b3883c7fd0ed9cd695c038bc
2006-12-26 01:43:18 -05:00
Nathan Binkert
2d029fe584 Make sure that all of the bits in the result are set
to some value.

--HG--
extra : convert_revision : 1f1700fd77531cbb8cfad7f04ce2b573fcdefdab
2006-12-24 15:15:12 -08:00
Nathan Binkert
e68a87e7fa remove some output formatting stuff that we don't use
--HG--
extra : convert_revision : 367917499d3d7aebd0a91dad28c915bc85def624
2006-12-24 14:06:56 -08:00
Nathan Binkert
91ffe811a3 Add options for setting the kernel to run and the
script to run

--HG--
extra : convert_revision : 32ad8e08ca74edf042d8606ca4876cbe1193e932
2006-12-22 21:51:19 -08:00
Nathan Binkert
139dcbe088 Fix copyright
--HG--
extra : convert_revision : 8ad7824885a5c4da80175c47ba5288aab55b06ca
2006-12-21 22:41:08 -08:00
Nathan Binkert
ecd1420341 Expose the C++ event queue to python via the python function
m5.internal.event.create().  It takes a python object and a
Tick and calls process() when the Tick occurs.

--HG--
extra : convert_revision : 5e4c9728982b206163ff51e6850a1497d85ad7a3
2006-12-21 22:38:50 -08:00
Nathan Binkert
ba191d85c2 style
--HG--
extra : convert_revision : 6bbaaa88a608081eebf706ff30293f38729415aa
2006-12-21 22:34:19 -08:00
Gabe Black
876c59fe8d Stub for SE mode gdb support for MIPS.
--HG--
extra : convert_revision : 2166b511c3615f7a2355f058a624e9ffe8259e65
2006-12-21 20:42:40 -05:00
Nathan Binkert
3f03e5f656 Create a wrapper function to more easily add swig stuff to the build
--HG--
extra : convert_revision : 3aaf540a9e314a88a8945579398f0d79aa85d5cf
2006-12-21 15:58:38 -08:00
Nathan Binkert
2cb2b50802 move the swig initialization calls from src/sim/main.cc to
src/python/swig/init.cc so that it's not as easy to forget
about it when you add a new swig module.

--HG--
extra : convert_revision : 5cc4ec0838e636aa761901effb8986de58d23e03
2006-12-21 15:49:16 -08:00
Nathan Binkert
9aecfb3e3b don't use (*activeThreads).begin(), use activeThreads->blah().
Also don't call (*activeThreads).end() over and over.  Just
call activeThreads->end() once and save the result.
Make sure we always check that there are elements in the list
before we grab the first one.

--HG--
extra : convert_revision : d769d8ed52da99532d57a9bbc93e92ddf22b7e58
2006-12-20 22:20:11 -08:00
Nathan Binkert
4b3538b609 Merge zizzer.eecs.umich.edu:/bk/newmem
into  iceaxe.:/Volumes/work/m5/incoming

--HG--
extra : convert_revision : c1724538f27091e16ca495c8fdf2df06f55f7668
2006-12-20 21:46:39 -08:00
Nathan Binkert
6487d358a4 <scold> Make sure that variables are always initalized! </scold>
--HG--
extra : convert_revision : 1e946d9b1e1def36f9b8a73986dabf1b77096327
2006-12-20 21:46:16 -08:00
Gabe Black
68a0e6f2e9 Fixes to get MIPS_SE to compile.
--HG--
extra : convert_revision : d173f212841341e436e9a38dcd3006d27886c1b8
2006-12-20 22:14:40 -05:00
Gabe Black
327f451eb7 Fixes to get ALPHA_FS and ALPHA_SE to compile again.
--HG--
extra : convert_revision : 6e0913903d4cbda6f31bec3b5d725b9c08dc1419
2006-12-20 20:44:06 -05:00
Gabe Black
f13155393d Initial work to make remote gdb available in SE mode. This is completely untested.
--HG--
extra : convert_revision : 3ad9a3368961d5e9e71f702da84ffe293fe8adc8
2006-12-20 18:39:40 -05:00
Gabe Black
841d76d37b Make sure the "stack_min" variable is page aligned.
--HG--
extra : convert_revision : e78c53778de83bdb2eca13d98d418b17b386ab29
2006-12-20 15:44:37 -05:00
Steve Reinhardt
6bc1e78d07 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 4bd4f8bb8e48e09562a2d9ae6eb7d061be973c5e
2006-12-19 02:11:48 -05:00
Ali Saidi
f27c686eb5 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : fa8ce7149973245a73bb562b9378db13be647a14
2006-12-19 02:11:47 -05:00
Ali Saidi
5e9d8795f2 fix twinx loads a little bit
bugfixes and demap implementation in tlb
ignore some more differencs for one cycle

src/arch/sparc/isa/formats/mem/blockmem.isa:
    twinx has 2 micro-ops
src/arch/sparc/isa/formats/mem/util.isa:
    fix the fault check for twinx
src/arch/sparc/tlb.cc:
    tlb bugfixes and write demapping code
src/cpu/exetrace.cc:
    don't halt on a couple more instruction (ldx, stx) when things differ
    beacuse of the way tlb faults are handled in legion.

--HG--
extra : convert_revision : 1e156dead6ebd58b257213625ed63c3793ef4b71
2006-12-19 02:11:33 -05:00
Steve Reinhardt
9d7db8bb2b Streamline Cache/Tags interface: get rid of redundant functions,
don't regenerate address from block in cache so that tags can
turn around and use address to look up block again.

--HG--
extra : convert_revision : 171018aa6e331d98399c4e5ef24e173c95eaca28
2006-12-18 23:07:52 -08:00
Steve Reinhardt
f655932700 No need to template prefetcher on cache TagStore type.
--HG--
rename : src/mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher.cc
extra : convert_revision : 56c0b51e424a3a6590332dba4866e69a1ad19598
2006-12-18 21:53:06 -08:00
Steve Reinhardt
1428b0de7d Get rid of generic CacheTags object (fold back into Cache).
--HG--
extra : convert_revision : 8769bd8cc358ab3cbbdbbcd909b2e0f1515e09da
2006-12-18 20:47:12 -08:00
Gabe Black
5b41ab694c Fix a place where the wrong width parameter was used, and set the nextNPC correctly on memory squashes.
--HG--
extra : convert_revision : 7914a48ea953607c48f93984e3b043098f0d7c62
2006-12-18 18:20:13 -05:00
Gabe Black
dfafe6741f Make sure you only handle branch delay slots specially when there actually was a branch.
--HG--
extra : convert_revision : ea6d33b1b9c2ba5c24225af4b10a9bd25558f1dd
2006-12-18 18:18:37 -05:00
Gabe Black
af1e8d2d40 Fixing the extended twin format to go with the new isa parser interface.
--HG--
extra : convert_revision : f41183cfa011b21e7ab8cbcdef0ac1d464692362
2006-12-18 18:17:30 -05:00
Nathan Binkert
0e78386874 Fix unittest compiles
--HG--
extra : convert_revision : 1163437081e1f1eab3f4512d04317dc94a673b9b
2006-12-18 14:08:42 -08:00
Nathan Binkert
9b40a13728 cast chars to int when we want to print integers so we get a number
instead of a character

--HG--
extra : convert_revision : 7bfa88ba23ad057b751eb01a80416d9f72cfe81a
2006-12-18 14:07:52 -08:00
Gabe Black
9e7dc34383 Merge zizzer.eecs.umich.edu:/.automount/zower/eecshome/m5/newmem
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/sparco3

--HG--
extra : convert_revision : f17800685609d8353ec14676f45fbb123fc4e6c3
2006-12-18 12:19:30 -05:00
Ali Saidi
6841f863c5 move the twinx loads to the correct opcode and add asis 0x24 and 0x27
Make the TLB ok to translate QUAD_LDD

src/arch/sparc/isa/decoder.isa:
    move the twinx loads to the correct opcode.
src/arch/sparc/tlb.cc:
    Make QUAD_LDD asi ok to execute

--HG--
extra : convert_revision : 2a44d1c9e4edb627079fc05776c28d918c8508ce
2006-12-18 03:37:52 -05:00
Steve Reinhardt
d19d7aa8a5 Minor cleanup of new snippet/subst code.
--HG--
extra : convert_revision : d81e0d1356f3433e8467e407d66d4afb95614748
2006-12-17 23:09:36 -08:00
Steve Reinhardt
968048f56a Convert Alpha (and finish converting MIPS) to new
InstObjParam interface.

src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/fp.isa:
src/arch/alpha/isa/int.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/isa/mem.isa:
src/arch/alpha/isa/pal.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/util.isa:
    Get rid of CodeBlock calls to adapt to new InstObjParam interface.
src/arch/isa_parser.py:
    Check template code for operands (in addition to snippets).
src/cpu/o3/alpha/dyn_inst.hh:
    Add (read|write)MiscRegOperand calls to Alpha DynInst.

--HG--
extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
2006-12-17 19:27:50 -08:00
Nathan Binkert
e65544b88b Nate's utility for compiling m5
--HG--
extra : convert_revision : 84b21f667736dfe07891323dcc810437ccb3c7c0
2006-12-17 18:58:50 -08:00
Nathan Binkert
2d09f30a6d Utilities for doing a format check for some elements of proper
m5 style and fixing whitespace.  For whitespace, any tabs in
leading whitespace on a line are converted to spaces, and any
trailing whitespace is removed.

--HG--
extra : convert_revision : d0591663c028a388635fc71c6c1d31f700748cf6
2006-12-17 18:58:05 -08:00
Gabe Black
c3ec52346b Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/operands.isa:
    Hand Merge

--HG--
extra : convert_revision : 4c54544e5c7a61f055ea9b00ccf5f8510df0e6c2
2006-12-17 11:55:24 -05:00
Gabe Black
81996f855a Compilation fixes.
--HG--
extra : convert_revision : 4932ab507580e0c9f7012398e71921ce58fc3c4e
2006-12-17 11:16:04 -05:00
Gabe Black
729dbb60e9 Added in the extended twin load format
src/arch/sparc/isa/decoder.isa:
    Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.

--HG--
extra : convert_revision : 5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
2006-12-17 11:15:37 -05:00
Gabe Black
c299c2562b Started removing "CodeBlock" objects from the mips isa description.
--HG--
extra : convert_revision : 2e174ecfce8c86732e1addfc23e961429b86a570
2006-12-17 10:54:17 -05:00
Gabe Black
220e99a29b Compilation fix after messy merge.
--HG--
extra : convert_revision : bf650dfe401377ce1b4c952aa8bfe3708c865472
2006-12-17 10:53:10 -05:00
Gabe Black
91b56d03fc Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/sparcfs

--HG--
extra : convert_revision : c8718b3df72b8c951c24742e8ce517a93bc23fe9
2006-12-16 12:55:55 -05:00
Gabe Black
c9f18981f9 Merge zizzer:/bk/sparcfs/
into  zower.eecs.umich.edu:/eecshome/m5/sparcfs

--HG--
extra : convert_revision : 2764b356ef01d1fcb6ed272e4ef96179cd651d4e
2006-12-16 12:55:15 -05:00
Gabe Black
b9d069167c Support for twin loads.
src/arch/sparc/isa/decoder.isa:
    Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
    Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
    Comment explaining twin load operands.

--HG--
extra : convert_revision : ad42821a97dcda17744875b1e5dc00a9642e59b7
2006-12-16 12:54:28 -05:00
Gabe Black
fe73760388 Compiler error fix.
--HG--
extra : convert_revision : 39e2638a10bf3e821e8f3d4d8c664008c98fc921
2006-12-16 12:53:01 -05:00