Commit graph

8306 commits

Author SHA1 Message Date
Ali Saidi
b5160ba2c3 ARM: Generate condition code setting code based on which codes are set.
This change further eliminates cases where condition codes were being read
just so they could be written without change because the instruction in
question was supposed to preserve them. This is done by creating the condition
code code based on the input rather than just doing a simple substitution.
2011-05-13 17:27:02 -05:00
Ali Saidi
05866c82f9 ARM: Construct the predicate test register for more instruction programatically.
If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.
2011-05-13 17:27:02 -05:00
Ali Saidi
401165c778 ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
2011-05-13 17:27:01 -05:00
Ali Saidi
e097c4fb18 ARM: Remove the saturating (Q) condition code from the renamed register.
Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
2011-05-13 17:27:01 -05:00
Ali Saidi
2178859b76 ARM: Break up condition codes into normal flags, saturation, and simd.
This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
2011-05-13 17:27:01 -05:00
Chander Sudanthi
4bf48a11ef Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.
Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and
ExecKernel are set by default when Exec is specified.  Use minus
sign with ExecUser or ExecKernel to remove user or kernel tracing
respectively.
2011-05-13 17:27:00 -05:00
Chander Sudanthi
5299c75e62 ARM: Better RealView/Versatile EB platform support.
Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
2011-05-13 17:27:00 -05:00
Geoffrey Blake
b79650ceaa O3: Fix an issue with a load & branch instruction and mem dep squashing
Instructions that load an address and are control instructions can
execute down the wrong path if they were predicted correctly and then
instructions following them are squashed. If an instruction is a
memory and control op use the predicted address for the next PC instead
of just advancing the PC. Without this change NPC is used for the next
instruction, but predPC is used to verify that the branch was successful
so the wrong path is silently executed.
2011-05-13 17:27:00 -05:00
Nathan Binkert
f7b3900c13 stats: delete mysql support
we can add it back within python in some future changeset
2011-05-12 11:19:35 -07:00
Nathan Binkert
1177e7a3c8 stats: move code that loops over all stats into python 2011-05-12 11:19:35 -07:00
Nathan Binkert
35b0c1d391 stats: better expose statistics to python.
Build a python list and dict of all stats and expose flags properly.

--HG--
rename : src/python/m5/stats.py => src/python/m5/stats/__init__.py
2011-05-12 11:19:32 -07:00
Nathan Binkert
9c4c1419a7 work around gcc 4.5 warning 2011-05-09 16:34:11 -04:00
Tushar Krishna
1267ff5949 NetworkTest: added sim_cycles parameter to the network tester.
The network tester terminates after injecting for sim_cycles
(default=1000), instead of having to explicitly pass --maxticks from the
command line as before. If fixed_pkts is enabled, the tester only
injects maxpackets number of packets, else it keeps injecting till sim_cycles.
The tester also works with zero command line arguments now.
2011-05-07 17:43:30 -04:00
Tushar Krishna
770f2ce330 network: added Torus and Pt2Pt topologies 2011-05-07 17:28:15 -04:00
Nilay Vaish
ffaef14466 Trace: Remove the options trace-help and trace-flags
The options trace-help and trace-flags are no longer required. In there place,
the options debug-help and debug-flags have been provided.
2011-05-07 07:38:36 -05:00
Gabe Black
b8889a96b3 X86: Fix the Lldt instructions so they load the ldtr and not the tr. 2011-05-06 01:00:32 -07:00
Korey Sewell
a0415f2b24 ruby: use RubyMemory flag & remove setDebug() functionality
The RubyMemory flag wasnt used in the code, creating large gaps in trace output. Replace cprintfs w/dprintfs
using RubyMemory in memory controller. DPRINTF also deprecate the usage of the setDebug() pure virtual
function in the AbstractMemoryOrCache Class as well the m_debug/cprintf functions in MemoryControl.hh/cc
2011-05-05 02:20:31 -04:00
Ali Saidi
fea2c26402 ARM: Update ARM_FS stats for mp changes 2011-05-04 20:38:28 -05:00
Ali Saidi
cefd6960e5 ARM: Configure bootloader parameters 2011-05-04 20:38:28 -05:00
Ali Saidi
42e7888855 ARM: Add support for loading the a bootloader and configuring parameters for it 2011-05-04 20:38:28 -05:00
Prakash Ramrakhyani
1b505f5291 ARM: Implement WFE/WFI/SEV semantics. 2011-05-04 20:38:28 -05:00
Ali Saidi
ba8d64520e ARM: Add support for MP misc regs and broadcast flushes. 2011-05-04 20:38:28 -05:00
Prakash Ramrakhyani
13574d8b4e ARM: Make GIC handle IPIs and multiple processors. 2011-05-04 20:38:27 -05:00
Ali Saidi
5f73d4ac97 ARM: Add snoop control unit device. 2011-05-04 20:38:27 -05:00
Ali Saidi
afd08879d7 ARM: Add support for some more registers in the real view controller. 2011-05-04 20:38:27 -05:00
Prakash Ramrakhyani
f738005266 ARM: Boot loader changes that make it more flexible about load and I/O addrs 2011-05-04 20:38:27 -05:00
Ali Saidi
307f089e7f O3/ARM: Update stats for recent changes. 2011-05-04 20:38:27 -05:00
Ali Saidi
8aff996db1 Debug: Add a function to cause the simulator to create a checkpoint from GDB. 2011-05-04 20:38:27 -05:00
Ali Saidi
77bea2fb42 CPU: Add some useful debug message to the timing simple cpu. 2011-05-04 20:38:27 -05:00
Ali Saidi
6e634beb8a CPU: Fix a case where timing simple cpu faults can nest.
If we fault, change the state to faulting so that we don't fault again in the same cycle.
2011-05-04 20:38:27 -05:00
Ali Saidi
89e7bcca82 O3: Remove assertion for case that is actually handled in code.
If an nonspeculative instruction has a fault it might not be in the
nonSpecInsts map.
2011-05-04 20:38:27 -05:00
Ali Saidi
974a776b31 Core: Add some documentation about the sim clocks. 2011-05-04 20:38:27 -05:00
Chris Emmons
8dcbf8576e RealView: Fix the 24 and 100MHz clocks which were providing incorrect values. 2011-05-04 20:38:26 -05:00
Ali Saidi
09a2be0c39 O3: Fix a small corner case with the lsq hazard detection logic. 2011-05-04 20:38:26 -05:00
Ali Saidi
48f7fda706 ARM: Add vfpv3 support to native trace. 2011-05-04 20:38:26 -05:00
Ali Saidi
632cf8dd80 ARM: Fix small bug with vcvt instruction 2011-05-04 20:38:26 -05:00
Nathan Binkert
0dffd35741 debug: fix help output 2011-05-04 10:08:08 -04:00
Steve Reinhardt
8ce85d3db6 scons: interpret paths relative to launch directory
Make sure all command-line targets and EXTRAS directories
are interpreted relative to the launch directory.  This
turns out to be very useful when building code from an
EXTRAS directory using SCons's -C option.

We were trying to do this with targets but it didn't actually
work since we didn't update BUILD_TARGETS (so SCons got
confused internally).  We weren't even trying with EXTRAS.

To simplify the code, the default target is also interpreted
relative to the launch dir even though it was explicitly
handled as relative to the m5 dir before... I doubt anyone
really uses this anyway so it didn't seem worth the complexity.
(Maybe we should get rid of it?)
2011-05-02 12:40:32 -07:00
Steve Reinhardt
f713af951a scons: allow use of current builds as default build settings
Currently the --default= option only looks at the predefined
build configs (in m5/build_opts), so you're limited to basing
a new build config off of those (ALPHA_SE, etc.).  If you've
already defined a non-standard build config and want to clone
it or tweak it, you have to start from scratch.  This patch
causes --default= to look first among the existing builds
(in build/variables) before looking in build_opts so you
can specify an existing non-standard build config as a
starting point for a new config.
2011-05-02 12:40:31 -07:00
Korey Sewell
dd95bc4d44 ruby: dbg: use system ticks instead of cycles 2011-05-02 00:16:14 -04:00
Gabe Black
947a5ba9a5 Util: Replace mkblankimage.sh with the new gem5img.py.
This change replaces the mkblankimage.sh script, used for creating new disk
images, with a new gem5img.py script. The new version is written in python
instead of bash, takes its parameters from command line arguments instead of
prompting for them, and finds a free loopback device dynamically instead of
hardcoding /dev/loop1. The file system used is now optionally configurable,
and the blank image is filled by a "hole" left by lseek and write instead of
literally filling it with zeroes.

The functionality of the new script is broken into subcommands "init",
"mount", "umount", "new", "partition", and "format". "init" creates a new file
of the appropriate size, partitions it, and then formats the first (and only)
new parition. "mount" attaches a new loopback device to the first parition of
the image file and mounts it to the specified mount point. "umount" unmounts
the specified mount point and identifies and cleans up the underlying loopback
device. "new", "partition", and "format" are the individual stages of "init"
but broken out so they can be run individually. That's so an image can be
reinitialized in place if needed.

Two features of the original script are being dropped. The first is the
ability to specify a source directory to copy into the new file system. The
second is the ability to specify a list of commands to run which are expected
to (but not required to) update the permissions of the files in the new fs.
Both of these seem easy enough to do manually, especially given the "mount"
and "umount" commands, that removing them would meaningfully simplify the
script without making it less useful.
2011-04-29 04:46:19 -04:00
Brad Beckmann
001c16bc6d regress: updates after changing ruby network bandwidth 2011-04-28 17:18:16 -07:00
Brad Beckmann
93a50fc318 network: set the ExtLink bw to 16 bytes
Therefore all links by default are 16 bytes wide and thus work with Garnet's
uniform link bandwidth assumption.
2011-04-28 17:18:14 -07:00
Brad Beckmann
6c7429dbe3 garnet: removed flit_width from Routers 2011-04-28 17:18:14 -07:00
Brad Beckmann
651cfbab03 network: adjusted default endpoint bandwidth
The simple network's endpoint bandwidth value is used to adjust the overall
bandwidth of the network.  Specifically, the ration between endpoint bandwidth
and the MESSAGE_SIZE_MULTIPLIER determines the increase.  By setting the value
to 1000, that means the bandwdith factor specified in the links translates to
the link bandwidth in bytes.  Previously, it was increasing that value by 10.

This patch will likely require a reset of the ruby regression tester stats.
2011-04-28 17:18:14 -07:00
Brad Beckmann
887e2df5a3 network: removed the unused network-wide latency param 2011-04-28 17:18:14 -07:00
Brad Beckmann
491cc1a9f4 network: moved network config params
Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of
the top-level parent network object and to only those networks that actually
use those parameters.
2011-04-28 17:18:14 -07:00
Brad Beckmann
8733ed4b7d network: basic link bw for garnet and simple networks
This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology.  To do so, the patch generalizes the specification
of bw for basic links.  This value is then translated to the specific value
used by the simple and Garnet networks.  Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.

--HG--
rename : src/mem/ruby/network/BasicLink.cc => src/mem/ruby/network/simple/SimpleLink.cc
rename : src/mem/ruby/network/BasicLink.hh => src/mem/ruby/network/simple/SimpleLink.hh
rename : src/mem/ruby/network/BasicLink.py => src/mem/ruby/network/simple/SimpleLink.py
2011-04-28 17:18:14 -07:00
Brad Beckmann
40bcbf4253 network: convert links & switches to first class C++ SimObjects
This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes.  This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.

--HG--
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
2011-04-28 17:18:14 -07:00
Brad Beckmann
bc5eb59605 garnet: cleaned up flexible network header file 2011-04-28 17:18:12 -07:00