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31 commits

Author SHA1 Message Date
Steve Reinhardt
97b6947eb7 Minor tweaks for future Ruby compatibility. 2009-04-21 08:17:36 -07:00
Korey Sewell
cf4a00ca41 Configs: Add support for the InOrder CPU model 2009-02-10 15:49:29 -08:00
Ali Saidi
f4291aac25 Errors: Print a URL with a hash of the format string to find more information about an error. 2009-01-30 20:04:15 -05:00
Ali Saidi
969688154d Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint doesn't exist 
--HG--
extra : convert_revision : c156c49668815755c4c788f807e8eba32151aa24
 2008-03-15 22:20:09 -04:00
Lisa Hsu
02a56d8d01 Error out if -s is used without --caches (instead of saying you must specify a 
CPU).

--HG--
extra : convert_revision : a3b2bfbe7e037146ac08dd08834bf255da692506
 2008-02-29 01:49:36 -05:00
Ali Saidi
0273533adb Configs: Make sure options don't conflict 
--HG--
extra : convert_revision : dc9b91cf1d8e33c5e68d7faeb45dbe3e7038d14c
 2008-02-29 01:23:18 -05:00
Ali Saidi
3cb7df428c Configs: Fix some bugs we introduced in the simpoints code 
--HG--
extra : convert_revision : ef22c11cb3242903a484fc05dc0f96d3e5f9af72
 2008-02-28 20:39:01 -05:00
Rick Strong
fcfc8b8c4f Configs: Make using Simpoints easier with some config files that support them easily 
--HG--
extra : convert_revision : 0f21829306eb68b332f03da410e6c341c8595bdd
 2008-02-27 00:35:09 -05:00
Vilas Sridharan
2e079ce038 add instruction count fast forwaing and max instruction options 
--HG--
extra : convert_revision : 8fe45e512229cdc3e0dcd23e3e5c54516c445d0f
 2008-02-22 17:48:10 -05:00
Ali Saidi
fc38e9c630 Configs: Change Simulation.py to return a subclass of the CPU models rather than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency. 
--HG--
extra : convert_revision : f972207c616590a60a6e103daa5de469cf124b44
 2008-02-14 16:13:50 -05:00
Ali Saidi
45ea1549c9 Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something. 
--HG--
extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
 2007-12-18 01:52:57 -05:00
Ali Saidi
5a4fc93fca Checkpoint: Use checkpoint_dir, if that is not set use outdir (-d), and if that isn't set use cwd. 
--HG--
extra : convert_revision : 6548dd6de376dd59285a37a03bcf2525f8fc3845
 2007-11-03 14:41:00 -04:00
Ali Saidi
51345d7324 Checkpoints: Change Simulation.py to not go crazy if the simulation ends before the number of checkpoints requested are created. 
--HG--
extra : convert_revision : 865179134a219b34dbbba698e1fa0da7c452e074
 2007-10-25 22:20:00 -04:00
Ali Saidi
136cb057d4 Checkpointing: Fix directory regex 
--HG--
extra : convert_revision : 4d3958eda66209373249e54e7deadd1a7442e828
 2007-09-12 15:27:15 -04:00
Ali Saidi
6f9ad931cc Checkpointing: Force drain/resume when switching a CPU 
--HG--
extra : convert_revision : 7d9c3f4c8c357e3a9214deba5df3581beeaf7cb6
 2007-09-12 15:24:24 -04:00
Nathan Binkert
d55b25cde6 Move all of the parameters of the Root SimObject so they are 
directly configured by python.  Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.

--HG--
extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
 2007-03-06 11:13:43 -08:00
Ali Saidi
3fa5816dcf fix some checkpointing annoyances 
-m works as you think it should
Ctrl-C actually ends the simulation now

--HG--
extra : convert_revision : f2269dc90d165c716459ec61f5f7b1ea3c1d4ae2
 2007-01-30 18:21:42 -05:00
Kevin Lim
07e525e8b7 Include check for making sure caches are enabled. 
--HG--
extra : convert_revision : e3902b065db524ebe5bf762e44a840133ccb8d75
 2006-11-26 11:46:58 -05:00
Kevin Lim
6591ebb098 Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : dafe2d4a032b277c219ea13faf20567c20c1f2f4
 2006-11-09 15:06:00 -05:00
Kevin Lim
0ba2cc6571 Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches. 
configs/common/Simulation.py:
    Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.

    However the O3CPU must always use caches, so a check for that must still exist.

    Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
    Atomic CPU now handles caches.

--HG--
extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e
 2006-11-09 15:05:13 -05:00
Lisa Hsu
64c0d82dec simplify maxtick parsing in both the python and the c++. 
configs/common/Simulation.py:
    simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
    make a new m5 param called MaxTick.
src/sim/host.hh:
    fix the M5 def. of MaxTick
src/sim/main.cc:
    Simplify the MaxTick/num_cycles parsing within main.cc

--HG--
extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668
 2006-11-08 15:05:23 -05:00
Lisa Hsu
0a0d9cd3ab change to os.path.join like nate wanted. 
--HG--
extra : convert_revision : 6e8a0153adf04f0cc07904434e4cb6a83fe900eb
 2006-11-08 14:01:23 -05:00
Lisa Hsu
74ff45d353 factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches. 
configs/common/Simulation.py:
    enable going from checkpoint into arbitrary CPU with or without caches.

--HG--
extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2
 2006-11-01 19:25:09 -05:00
Lisa Hsu
7665be4f70 make it so that you can do a standard switch without the caches option. this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache. 
--HG--
extra : convert_revision : d733de7ebb362bbd7376a0235ee7f117df2d6d37
 2006-11-01 11:49:39 -05:00
Lisa Hsu
9ef8bf74c7 change name of 2nd switch_cpu so that ckpt recovery with multiple cpus doens't get confused. 
--HG--
extra : convert_revision : 16c710c4196c520d03c1993a26f38cf1f04ab637
 2006-11-01 11:40:49 -05:00
Kevin Lim
f763864786 Fix up configs. 
configs/common/Simulation.py:
    Remove mem parameter.
configs/example/se.py:
    Remove debug output that got included in my other push.

--HG--
extra : convert_revision : 643c34147f6c6cbb98b8e6d6e8206b9859593ab0
 2006-10-31 14:58:09 -05:00
Lisa Hsu
580c8421ab se.py, fs.py: 
import Caches
Simulation.py:
Fix typo - L2Cache --> L1Cache

configs/common/Simulation.py:
    Fix typo - L2Cache --> L1Cache
configs/example/fs.py:
configs/example/se.py:
    import Caches

--HG--
extra : convert_revision : 4292225b322c069665262eab7c83b5341844fba0
 2006-10-30 16:51:46 -05:00
Lisa Hsu
fe2698c435 ensure that there is a "/" between the cptdir and the cpt.%d. 
--HG--
extra : convert_revision : 9aed7c3aecad10b039f3cfb26e04a7950be6bed1
 2006-10-30 14:19:16 -05:00
Lisa Hsu
883f0394f5 decouple the switch option from the warmup period option - parsing was confused otherwise, oops. 
--HG--
extra : convert_revision : 951fc664c59363df5f5e026aa791d83c26f050ec
 2006-10-30 14:12:15 -05:00
Lisa Hsu
b40af2328a add some comments and make the warmup period in a switchover parameterizable. 
configs/common/Options.py:
    make the warmup period in a standard switch part of the option.
configs/common/Simulation.py:
    add some comments and also make the warmup period an option.

--HG--
extra : convert_revision : 0fa587291b97ff87c3b3a617e7359ac6d9bed7a5
 2006-10-30 13:33:27 -05:00
Lisa Hsu
a6fd29ddf9 factor out common run code from se.py and fs.py. 
configs/example/fs.py:
    factor out common code.
configs/example/se.py:
    factor out common code

--HG--
extra : convert_revision : 72a1f653c84eae1b7d281e0a5e60ee116ad6b27d
 2006-10-27 16:32:26 -04:00