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10095 commits

Author SHA1 Message Date
Andreas Hansson
a0e551869c config: Remove Clock parameter multiplication
This patch removes the multiplication operator support for Clock
parameters as this functionality is now achieved by creating derived
clock domains.

Nate, this one is for you.
2013-06-27 05:49:50 -04:00
Akash Bagdia
7d7ab73862 sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.

The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).

The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.

All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.

The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 05:49:49 -04:00
Andreas Hansson
4de3205afa config: Add a BaseSESystem builder for re-use in regressions
This patch extends the existing system builders to also include a
syscall-emulation builder. This builder is deployed in all
syscall-emulation regressions that do not involve Ruby,
i.e. o3-timing, simple-timing and simple-atomic, as well as the
multi-processor regressions o3-timing-mp, simple-timing-mp and
simple-atomic-mp (the latter are only used by SPARC at this point).

The values chosen for the cache sizes match those that were used in
the existing config scripts (despite being on the large
side). Similarly, a mem_class parameter is added to the builder base
class to enable simple-atomic to use SimpleMemory and o3-timing to use
the default DDR3 configuration.

Due to the different order the ports are connected, the bus stats get
shuffled around for the multi-processor regressions. A separate patch
bumps the port indices. Besides this, all behaviour is exactly the
same.
2013-06-27 05:49:49 -04:00
Akash Bagdia
597d2aa3a6 config: Rename clock option to Ruby clock
This patch changes the 'clock' option to 'ruby-clock' as it is only
used by Ruby.
2013-06-27 05:49:49 -04:00
Akash Bagdia
076d04a653 config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.

As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.

The configs and tests are updated accordingly.
2013-06-27 05:49:49 -04:00
Akash Bagdia
4459b30525 config: Add a CPU clock command-line option
This patch adds a 'cpu_clock' command-line option and uses the value
to assign clocks to components running at the CPU speed (L1 and L2
including the L2-bus). The configuration scripts are updated
accordingly.

The 'clock' option is left unchanged in this patch as it is still used
by a number of components. In follow-on patches the latter will be
disambiguated further.
2013-06-27 05:49:49 -04:00
Akash Bagdia
7eccb1b779 config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
2013-06-27 05:49:49 -04:00
Andreas Hansson
f821c5472b tests: Prune 00.gzip from the regressions
This patch prunes the 00.gzip regressions with the main motivation
being that it adds little (or no) coverage and requires a substantial
amount of run time.

A complete regression run, including compilation from a clean repo, is
almost 20% faster(!).
2013-06-27 05:49:49 -04:00
Andreas Hansson
3b92748937 mem: Tidy up the bridge with const and additional checks
This patch does a bit of tidying up in the bridge code, adding const
where appropriate and also removing redundant checks and adding a few
new ones.

There are no changes to the behaviour of any regressions.
2013-06-27 05:49:49 -04:00
Andreas Hansson
f25ea3fd56 mem: Fix CommMonitor style and response check
This patch fixes the CommMonitor local variable names, and also
introduces a variable to capture if it expects to see a response. The
latter check considers both needsResponse and memInhibitAsserted.
2013-06-27 05:49:49 -04:00
Andreas Hansson
33a8d777ad mem: Align cache timing to clock edges
This patch changes the cache timing calculations such that the results
are aligned to clock edges.

Plenty stats change as a results of this patch.
2013-06-27 05:49:49 -04:00
Andreas Hansson
10650fc525 cpu: Consider instructions waiting for FU completion in draining
This patch changes the IEW drain check to include the FU pool as there
can be instructions that are "stored" in FU completion events and thus
not covered by the existing checks. With this patch, we simply include
a check to see if all the FUs are considered non-busy in the next
tick.

Without this patch, the pc-switcheroo-full regression fails after
minor changes to the cache timing (aligning to clock edge).
2013-06-27 05:49:49 -04:00
Andreas Hansson
368f50a0a1 mem: Cycles converted to Ticks in atomic cache accesses
This patch fixes an outstanding issue in the cache timing calculations
where an atomic access returned a time in Cycles, but the port
forwarded it on as if it was in Ticks.

A separate patch will update the regression stats.
2013-06-27 05:49:49 -04:00
Andreas Hansson
718fb40709 scons: Identify runs that fail and runs with stats differences
This patch changes the regression script such that it is possible to
identify the runs that fail with an exit code, and those that finish
with stats differences. The ones that truly fail are reported as
FAILED, and those that finish with changed stats as CHANGED.

The yellow colour has been reclaimed from the skipped regressions and
is now used for the changed ones. With no obvious good option left the
skipped ones are now in cyan.

While I was editing the script I also bumped any occurence of M5 to
gem5.
2013-06-27 05:49:49 -04:00
Andreas Hansson
997a6a4add base: Fix address range granularity calculation
This patch fixes a bug in the granularity calculation. For example, if
the high bit is 6 (counting from 0) and we have one interleaving bit,
then the granularity is now 2 ** (6 - 1 + 1) = 64.
2013-06-27 05:49:49 -04:00
Andreas Hansson
f330b3c28d mem: Remove a redundant heap allocation for a snoop packet
This patch changes the updards snoop packet to avoid allocating and
later deleting it. As the code executes in 0 time and the lifetime of
the packet does not extend beyond the block there is no reason to heap
allocate it.
2013-06-27 05:49:49 -04:00
Andreas Hansson
9a1169f3d7 mem: Remove CoherentBus snoop port unused private member
This patch removes an unused member to avoid getting compiler warnings
when using clang.
2013-06-27 05:49:49 -04:00
Sascha Bischoff
3d19bccb93 stats: Remove printing of SparseHist total
This patch removes the printing of the SparseHist total in the
stats.txt output file. This has been removed as a sparse histogram has
no total, and therefore this was printing out the value of a
non-local, unrelated variable.
2013-06-27 05:49:49 -04:00
Nilay Vaish
a1e18270a1 stats: updates due to changes to stat collection in ruby 2013-06-25 00:32:04 -05:00
Nilay Vaish
d8ed1d1a2c ruby: moesi cmp directory: separate actions for external hits
This patch adds separate actions for requests that missed in the local cache
and messages were sent out to get the requested line. These separate actions
are required for differentiating between the hit and miss latencies in the
statistics collected.
2013-06-25 00:32:04 -05:00
Nilay Vaish
128ab50c47 ruby: mesi cmp directory: separate actions for external hits
This patch adds separate actions for requests that missed in the local cache
and messages were sent out to get the requested line. These separate actions
are required for differentiating between the hit and miss latencies in the
statistics collected.
2013-06-25 00:32:03 -05:00
Nilay Vaish
beb6e57c6f ruby: profiler: lots of inter-related changes
The patch started of with removing the global variables from the profiler for
profiling the miss latency of requests made to the cache. The corrresponding
histograms have been moved to the Sequencer. These are combined together when
the histograms are printed. Separate histograms are now maintained for
tracking latency of all requests together, of hits only and of misses only.

A particular set of histograms used to use the type GenericMachineType defined
in one of the protocol files. This patch removes this type. Now, everything
that relied on this type would use MachineType instead. To do this, SLICC has
been changed so that multiple machine types can be declared by a controller
in its preamble.
2013-06-25 00:32:03 -05:00
Andreas Hansson
beee57070a stats: Bump x86 stats
This patch bumps the x86 stats to reflect the recent fixes.
2013-06-24 14:17:22 -04:00
Nilay Vaish
b3db882dee ruby: remove the three files related to profiling
This patch removes the following three files: RubySlicc_Profiler.sm,
RubySlicc_Profiler_interface.cc and RubySlicc_Profiler_interface.hh.
Only one function prototyped in the file RubySlicc_Profiler.sm. Rest of the
code appearing in any of these files is not in use. Therefore, these files
are being removed.

That one single function, profileMsgDelay(), is being moved to the protocol
files where it is in use. If we need any of these deleted functions, I think
the right way to make them visible is to have the AbstractController class in
a .sm and let the controller state machine inherit from this class. The
AbstractController class can then have the prototypes of these profiling
functions in its definition.
2013-06-24 08:59:08 -05:00
Joel Hestness ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
71c6c43110 ruby: MessageBuffer: Remove unused m_size variable
The m_size variable attempted to track m_prio_heap.size(), but it did so
incorrectly due to the functions reanalyzeMessages and reanalyzeAllMessages().
Since this variable is intended to track m_prio_heap.size(), we can simply
replace instances where m_size is referenced with m_prio_heap.size(), which
has the added bonus of removing the need for m_size.

Note: This patch also removes an extraneous DPRINTF format string designator
from reanalyzeAllMessages()

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-06-24 06:57:06 -05:00
Lena Olson
94280c7e51 ruby: fix typo in MOESI_CMP_token protocol 2013-06-20 16:20:38 -05:00
Lena Olson
ed234ddec6 ruby: Fix prefetching for MESI_CMP_Directory
Transitions from present on PF_Ifetch were missing, causing a crash when
prefetching is enabled.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-06-18 16:59:22 -05:00
Lena Olson
eb1279ff49 ruby: fix slicc compiler to complain about duplicate symbols
Previously, .sm files were allowed to use the same name for a type and a
variable. This is unnecessarily confusing and has some bad side effects, like
not being able to declare later variables in the same scope with the same type.
This causes the compiler to complain and die on things like Address Address.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-06-18 16:58:52 -05:00
Lena Olson
7c39d5df7e ruby: restrict Address to being a type and not a variable name
Change all occurrances of Address as a variable name to instead use Addr.
Address is an allowed name in slicc even when Address is also being used as a
type, leading to declarations of "Address Address". While this works, it
prevents adding another field of type Address because the compiler then thinks
Address is a variable name, not type.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-06-18 16:58:33 -05:00
Andreas Sandberg
d06064c386 x86: Add support for maintaining the x87 tag word
The current implementation of the x87 never updates the x87 tag
word. This is currently not a big issue since the simulated x87 never
checks for stack overflows, however this becomes an issue when
switching between a virtualized CPU and a simulated CPU. This
changeset adds support, which is enabled by default, for updating the
tag register to every floating point microop that updates the stack
top using the spm mechanism.

The new tag words is generated by the helper function
X86ISA::genX87Tags(). This function is currently limited to flagging a
stack position as valid or invalid and does not try to distinguish
between the valid, zero, and special states.
2013-06-18 16:36:08 +02:00
Andreas Sandberg
a8e8c4f433 x86: Fix loading of floating point constants
This changeset actually fixes two issues:

 * The lfpimm instruction didn't work correctly when applied to a
   floating point constant (it did work for integers containing the
   bit string representation of a constant) since it used
   reinterpret_cast to convert a double to a uint64_t. This caused a
   compilation error, at least, in gcc 4.6.3.

 * The instructions loading floating point constants in the x87
   processor didn't work correctly since they just stored a truncated
   integer instead of a double in the floating point register. This
   changeset fixes the old microcode by using lfpimm instruction
   instead of the limm instructions.
2013-06-18 16:30:06 +02:00
Andreas Sandberg
c9c02efb99 x86: Initialize the MXCSR register 2013-06-18 16:28:36 +02:00
Andreas Sandberg
688fc7f71f x86: Make the boot state VMX compliant
This patch allows the default x86 state to be used when by CPUs that
use hardware virtualization.
2013-06-18 16:27:28 +02:00
Andreas Sandberg
5d584934ad x86: Make fprem like the fprem on a real x87
The current implementation of fprem simply does an fmod and doesn't
simulate any of the iterative behavior in a real fprem. This isn't
normally a problem, however, it can lead to problems when switching
between CPU models. If switching from a real CPU in the middle of an
fprem loop to a simulated CPU, the output of the fprem loop becomes
correupted. This changeset changes the fprem implementation to work
like the one on real hardware.
2013-06-18 16:10:42 +02:00
Andreas Sandberg
6151c0f7f4 kvm: Use the address finalization code in the TLB
Reuse the address finalization code in the TLB instead of replicating
it when handling MMIO. This patch also adds support for injecting
memory mapped IPR requests into the memory system.
2013-06-18 16:10:22 +02:00
Andreas Sandberg
46a8cbbb7f x86: Add helper functions to access rflags
The rflags register is spread across several different registers. Most
of the flags are stored in MISCREG_RFLAGS, but some are stored in
microcode registers. When accessing RFLAGS, we need to reconstruct it
from these registers. This changeset adds two functions,
X86ISA::getRFlags() and X86ISA::setRFlags(), that take care of this
magic.
2013-06-18 16:10:22 +02:00
Andreas Sandberg
de89e133d8 x86: Fix the flag handling code in FABS and FCHS
This changeset fixes two problems in the FABS and FCHS
implementation. First, the ISA parser expects the assignment in
flag_code to be a pure assignment and not an and-assignment, which
leads to the isa_parser omitting the misc reg update. Second, the FCHS
and FABS macro-ops don't set the SetStatus flag, which means that the
default micro-op version, which doesn't update FSW, is executed.
2013-06-18 16:10:21 +02:00
Nilay Vaish
59befdb628 Added tag stable_2013_06_16 for changeset 07352f119e48 2013-06-16 08:27:42 -05:00
Nilay Vaish
be981772b9 config: Do not instantiate membus when using ruby
This patch moves the instantiation of system.membus in se.py to the area of
code where classic memory system has been dealt with. Ruby does not require
this bus and hence it should not be instantiated.
2013-06-13 07:24:25 -05:00
Andreas Sandberg
64270b19c3 kvm: Add more VM stats
This changeset adds the following stats to KVM:
 * numVMHalfEntries: Number of entries into KVM to finalize pending
   IO operations without executing guest instructions. These typically
   happen as a result of a drain where the guest must finalize some
   operations before the guest state is consistent.
 * numExitSignal: Number of VM exits that have been triggered by a
   signal. These usually happen as a result of the timer that limits
   the time spent in KVM.
2013-06-11 09:43:05 +02:00
Andreas Sandberg
c97a99110b kvm: Separate host frequency from simulated CPU frequency
We used to use the KVM CPU's clock to specify the host frequency. This
was not ideal for several reasons. One of them being that the clock
parameter of a CPU determines the frequency of some of the components
connected to the CPU. This changeset adds a separate hostFreq
parameter that should be used to specify the host frequency until we
add code to autodetect it. The hostFactor should still be used to
specify the conversion factor between the host performance and that of
the simulated system.
2013-06-11 09:24:55 +02:00
Andreas Sandberg
4f002930bc kvm: Don't handle IO and execute in the same tick
We currently execute instructions in the guest and then handle any IO
request right after we break out of the virtualized environment. This
has the effect of executing IO requests in the exact same tick as the
first instruction in the sequence that was just run. There seem to be
cases where this simplification upsets some timing-sensitive devices.

This changeset splits execute and IO (and other services) across
multiple ticks. This is implemented by adding a separate
RunningService state to the CPU state machine. When a VM requires
service, it enters into this state and pending IO is then serviced in
the future instead of immediately. The delay between getting the
request and servicing it depends on the number of cycles executed in
the guest, which allows other components to catch up with the CPU.
2013-06-11 09:24:51 +02:00
Andreas Sandberg
df059f45a0 kvm: Maintain a local instruction counter and update totalNumInsts
Update the system's totalNumInst counter when exiting from KVM and
maintain an internal absolute instruction count instead of relying on
the one from perf.
2013-06-11 09:24:40 +02:00
Andreas Sandberg
0b4a8b4086 x86: Fix bug when copying TSC on CPU handover
The TSC value stored in MISCREG_TSC is actually just an offset from
the current CPU cycle to the actual TSC value. Writes with
side-effects to the TSC subtract the current cycle count before
storing the new value, while reads add the current cycle count. When
switching CPUs, the current value is copied without side-effects. This
works as long as the source and the destination CPUs have the same
clock frequencies. The TSC will jump, sometimes backwards, if they
have different clock frequencies. Most OSes assume the TSC to be
monotonic and break when this happens.

This changeset makes sure that the TSC is copied with side-effects to
ensure that the offset is updated to match the new CPU.
2013-06-11 09:24:38 +02:00
Andreas Sandberg
2442aae54f sim: Revert [34e3295b0e39] (sim: Fix early termination in mult...)
HG changset 34e3295b0e39 introduced a check in the main simulation
loop that discards exit events that happen at the same tick as another
exit event. This was supposed to fix a problem where a simulation
script got confused by multiple exit events. This obviously breaks the
simulator since it can hide important simulation events, such as a
simulation failure, that happen at the same time as a non-fatal
simulation event.
2013-06-11 09:24:10 +02:00
Andreas Sandberg
0793d0727b cpu: Add support for scheduling multiple inst/load stop events
Currently, the only way to get a CPU to stop after a fixed number of
instructions/loads is to set a property on the CPU that causes a
SimLoopExitEvent to be scheduled when the CPU is constructed. This is
clearly not ideal in cases where the simulation script wants the CPU
to stop at multiple instruction counts (e.g., SimPoint generation).

This changeset adds the methods scheduleInstStop() and
scheduleLoadStop() to the BaseCPU. These methods are exported to
Python and are designed to be used from the simulation script. By
using these methods instead of the old properties, a simulation script
can schedule a stop at any point during simulation or schedule
multiple stops. The number of instructions specified when scheduling a
stop is relative to the current point of execution.
2013-06-11 09:18:25 +02:00
Nilay Vaish
247e4e9ab4 stats: updates due to changes to ruby
Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.
2013-06-10 06:46:20 -05:00
Nilay Vaish
d32ee94231 ruby: remove several unused variables in Profiler
This patch removes per processor cycle count, histogram for filter stats,
histogram for multicasts, histogram for prefetch wait, some function
prototypes that do not have definitions.
2013-06-09 07:30:00 -05:00
Nilay Vaish
27b321f2f7 ruby: remove periodic event from Profiler
The Profiler class does not need an event for dumping statistics
periodically. This is because there is a method for dumping statistics
for all the sim objects periodically. Since Ruby is a sim object, its
statistics are also included.
2013-06-09 07:29:59 -05:00
Nilay Vaish
f59a7af50a ruby: stats: use gem5's stats for cache and memory controllers
This moves event and transition count statistics for cache controllers to
gem5's statistics. It does the same for the statistics associated with the
memory controller in ruby.

All the cache/directory/dma controllers individually collect the event and
transition counts. A callback function, collateStats(), has been added that
is invoked on the controller version 0 of each controller class. This
function adds all the individual controller statistics to a vector
variables. All the code for registering the statistical variables and
collating them is generated by SLICC. The patch removes the files
*_Profiler.{cc,hh} and *_ProfileDumper.{cc,hh} which were earlier used for
collecting and dumping statistics respectively.
2013-06-09 07:29:59 -05:00