arch/alpha/alpha_linux_process.cc:
add endian conversions for fstat functions
arch/alpha/alpha_tru64_process.cc:
add endian conversions for various functions
sim/byteswap.hh:
for some reason gcc on macos really wants long and unsigned long
Why int32_t and uint32_t isn't sufficient I don't know.
sim/process.cc:
sim/syscall_emul.hh:
endian fixes
--HG--
extra : convert_revision : ce625d5660b70867c43c74fbed856149c0d8cd36
arch/alpha/main.isa to test my files ...
arch/mips/isa/operands.isa:
use sd and ud instead of sdw and udw
--HG--
extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
SConscript:
Moved pseudo_inst.hh from targetarch to full system sources
arch/alpha/SConscript:
Moved pseudo_inst.cc out of the alpha specific sources
arch/alpha/isa/decoder.isa:
The decoder now pulls out the arguments for the pseudo instructions based on the alpha ABI
arch/alpha/isa/main.isa:
Registers 16, 17 and 18 are used to get parameters for the pseudo instructions and can be referred to explicitly
sim/pseudo_inst.cc:
Changed some include paths to reflect that pseudo_inst.hh is now outside of the alpha directory. Also, instead of extracting their parameters directly, they're passed in as regular function arguments.
sim/pseudo_inst.hh:
Changed the function prototypes to include the functions parameters, now that they aren't extracted from the execution context.
--HG--
rename : arch/alpha/pseudo_inst.cc => sim/pseudo_inst.cc
rename : arch/alpha/pseudo_inst.hh => sim/pseudo_inst.hh
extra : convert_revision : 76ce768cf1d8a838aa7b64878a7ab4c4215ac999
SConscript:
Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh
targetarch/isa_traits.hh is now included through arch/isa_traits.hh
vptr.hh was removed from targetarch, and moved to sim
arch/alpha/pseudo_inst.cc:
Moved vptr.hh from targetarch to sim
base/loader/object_file.hh:
base/loader/symtab.hh:
cpu/base.hh:
dev/ide_disk.cc:
Changed the include of isa_traits.hh from targetarch to arch
cpu/static_inst.hh:
dev/platform.hh:
dev/simple_disk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/mbuf.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/process.hh:
sim/syscall_emul.hh:
Changed the include of isa_traits.hh from targetarch to arch.
kern/linux/linux_threadinfo.hh:
Changed the include of vptr.hh from targetarch to sim.
sim/byteswap.hh:
Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t)
sim/vptr.hh:
Fixed the assert in the equals operator.
Changed the AlphaISA namespace reference to TheISA.
Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures.
Added an include of arch/isa_traits.hh so that TheISA would be defined.
--HG--
extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
minor change to syntax of 'def operands' in ISA descriptions.
arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
Change 'def operands' statement to work with new
isa_parser changes.
arch/isa_parser.py:
Merge OperandTraits and OperandDescriptor objects into a
unified hierarchy of Operand objects.
Required a change in the syntax of the 'def operands'
statement in the ISA description.
--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
arch/isa_parser.py:
Minor cleanup of operand type and traits code:
- build operand size map right away when types are defined
instead of waiting to do it lazily
- check that operand types have been defined before operands
- don't use 'type' as a variable name
- use isinstance() instead of checking for types directly
--HG--
extra : convert_revision : 099c1ee8d490f9c38316749bf87209388c55c971
instruction format functions in ISA description language.
Take advantage of these features to clean up memory
instruction definitions in Alpha.
arch/alpha/isa/decoder.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
Take advantage of new keyword parameters to disambiguate
instruction vs. memory-request flags, and to provide
a default EA calculation for memory ops (since 99% of them
are the same).
arch/isa_parser.py:
Add two new features to instruction format functions:
- Keyword parameters, a la Python.
- List-valued arguments.
Also export makeList() function to Python code blocks,
as this is handy for dealing with flags.
--HG--
extra : convert_revision : 99bbbaa2e765230aa96b6a06ed193793325f9fb0
wrong
arch/alpha/alpha_linux_process.cc:
fix #if. I wonder why my compiler had no issues
--HG--
extra : convert_revision : 880a0442b28811db5ec548ce940060d4b26ec634
arch/alpha/alpha_linux_process.cc:
Add endian conversions to fstat
sim/byteswap.hh:
for some reason I don't understand g++ really wanted a long version defined
even though int32_t should be the same.
--HG--
extra : convert_revision : 5bfe9d3f0b31824fa5a7ae3f51fd0be5ed4d555d
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
fixup for bsd hosts. Some headers are included by default which means that
more variables need TGT_ prefixes and there isn't a stat call (everything
is a stat64 call) so we have to work around that a bit
base/intmath.hh:
base/socket.cc:
this is no longer needed with mac os 10.4
cpu/inst_seq.hh:
just use a uint64_t instead of long long
cpu/o3/inst_queue_impl.hh:
I much cleaner way to get max int
sim/syscall_emul.hh:
fix stat64 problems on *BSD
--HG--
extra : convert_revision : 9eef5f896e083ae1774e818a9765dd83e0305942
Should enable implementation of split-phase timing loads
with new memory model.
May create slight timing differences under FullCPU, as I
believe we were not handling software prefetches correctly
before when the split MemAcc/Exec model was used. I haven't
looked into this in any detail though.
arch/alpha/isa/decoder.isa:
HwLoadStore format split into separate HwLoad and
HwStore formats.
Copy instructions now fall under MiscPrefetch format.
Mem_write_result is now just write_result in store
conditionals.
arch/alpha/isa/mem.isa:
Split MemAccExecute and LoadStoreExecute templates
into separate templates for loads and stores; now
that memory operands are handled differently from
registers, it's impossible to have a single template
serve both.
Also unified the handling of "regular" prefetches
(loads to r31) and "misc" prefetches (e.g., wh64)
under the new scheme. It looks like SW prefetches
were not handled correctly in FullCPU up til now,
since we generated an execute() method for the outer
instruction but didn't generate a proper method for
MemAcc::execute() (instead getting a default no-op
method for that).
arch/alpha/isa/pal.isa:
Split HwLoadStore into separate HwLoad and HwStore
formats to select proper template (see change to
mem.isa in this changeset).
arch/isa_parser.py:
Stop trying to treat memory operands like register
operands, since we never used them in a uniform way
anyway, and it made it impossible to do split-phase
loads as needed for the new CPU model. Now there's no
more 'op_mem_rd', 'op_nonmem_rd', etc.: 'op_rd' just does
register operands, and the template code is responsible
for formulating the call to the memory system. Right now
the only thing exported by InstObjParams is a new attribute
'mem_acc_size' which gives the memory access size in bits,
though more attributes can be added if needed.
Also moved code in findOperands() method to
OperandDescriptorList.__init__(), which is where it belongs.
--HG--
extra : convert_revision : 6d53d07e0c5e828455834ded4395fa40f9146a34
=================================================
-every MIPS32 ISA is represented with some type
of code block.
-any instruction that doesnt have a code block
would be of format WarnUnimpl. Examples of the
ones I am waiting on further info to implement
are the TLB register insts, memory consistency
instructions (ll,sc,etc.) and software debug
insts.
--HG--
extra : convert_revision : 4a26c72e4fa1f63b8689fe2631a7508daf660969
(thanks to Gabe's include feature!).
arch/alpha/isa/main.isa:
Split out into multiple .isa files.
--HG--
extra : convert_revision : 30d8edf74ea194d4a208febf1e66edc72a7dbd5d
arch/isa_parser.py:
Clean up ##include code a bit.
arch/sparc/isa/formats.isa:
arch/sparc/isa/main.isa:
Fix include paths.
--HG--
extra : convert_revision : 0689963c2948e5f1088ecbf2cf6018d29bdaceff
arch/isa_parser.py:
Get rid of "munged name" for operands in C++ code.
That is, "Ra.uq" will now be known in the C++ as "Ra"
rather than "Ra_uq". It wasn't legal to use different
type extensions for the same operand at the same time
anyway, and now it will be easier to refer to explicit
operands in template code if necessary.
--HG--
extra : convert_revision : 9ff41e0201aeefe761743084ecdb34f4b9c84fdb
SConscript:
Changed the ISAPath function to take 5 arguments to work with scons 0.97.
--HG--
extra : convert_revision : 34fbe131aec9349631b5026d839563380623f3fd
arch/mips/isa/decoder.isa:
Code for di,ei,seb,seh,clz,and clo ....
Every instruction has a format now (of course these are initial formats are still subject to change!)
arch/mips/isa/formats/branch.isa:
Format Branch in MIPS similar to Alpha Format
--HG--
extra : convert_revision : 2118a1d9668610b1e9f1dea66d878b7b36c1ac7e
with isPowerOf2() from intmath.hh.
base/sched_list.hh:
Use isPowerOf2() from intmath.hh.
--HG--
extra : convert_revision : 7b2409531d8ed194aa7e1cfcd1ecb8460c797a16
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
Replaced the namespace declaration with including arch/alpha/isa_traits.hh
--HG--
extra : convert_revision : 07cb73a9f30f0e165809668f9baff6a3e3f94580
SConscript:
Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
Added MIPS as a valid architecture
cpu/exec_context.hh:
Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.
--HG--
extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007
The extra class is needed because of the necessisty of an immediate member variable.
Also, added some 'very modest' python code to choose between the IntOp and
the IntImmOp based on the instruction name ...
--HG--
extra : convert_revision : f109c12418202a99b40e270360134e8335739836
arch/mips/isa/formats/int.format:
Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from
their reg-reg counterparts
--HG--
rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa
rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa
rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa
extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
Output,Format, & Template code needs to be adjusted to correctly take these "decoder.h" inputs ...
--HG--
extra : convert_revision : 3dcde1f2f587e2766fd61231a93d34d1d7727356
