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Steve Reinhardt 3923eec0ef Change how memory operands are handled in ISA descriptions. 
Should enable implementation of split-phase timing loads
with new memory model.
May create slight timing differences under FullCPU, as I
believe we were not handling software prefetches correctly
before when the split MemAcc/Exec model was used.  I haven't
looked into this in any detail though.

arch/alpha/isa/decoder.isa:
    HwLoadStore format split into separate HwLoad and
    HwStore formats.
    Copy instructions now fall under MiscPrefetch format.
    Mem_write_result is now just write_result in store
    conditionals.
arch/alpha/isa/mem.isa:
    Split MemAccExecute and LoadStoreExecute templates
    into separate templates for loads and stores; now
    that memory operands are handled differently from
    registers, it's impossible to have a single template
    serve both.
    Also unified the handling of "regular" prefetches
    (loads to r31) and "misc" prefetches (e.g., wh64)
    under the new scheme.  It looks like SW prefetches
    were not handled correctly in FullCPU up til now,
    since we generated an execute() method for the outer
    instruction but didn't generate a proper method for
    MemAcc::execute() (instead getting a default no-op
    method for that).
arch/alpha/isa/pal.isa:
    Split HwLoadStore into separate HwLoad and HwStore
    formats to select proper template (see change to
    mem.isa in this changeset).
arch/isa_parser.py:
    Stop trying to treat memory operands like register
    operands, since we never used them in a uniform way
    anyway, and it made it impossible to do split-phase
    loads as needed for the new CPU model.  Now there's no
    more 'op_mem_rd', 'op_nonmem_rd', etc.: 'op_rd' just does
    register operands, and the template code is responsible
    for formulating the call to the memory system.  Right now
    the only thing exported by InstObjParams is a new attribute
    'mem_acc_size' which gives the memory access size in bits,
    though more attributes can be added if needed.

    Also moved code in findOperands() method to
    OperandDescriptorList.__init__(), which is where it belongs.

--HG--
extra : convert_revision : 6d53d07e0c5e828455834ded4395fa40f9146a34
2006-02-10 09:12:55 -05:00
arch Change how memory operands are handled in ISA descriptions. 2006-02-10 09:12:55 -05:00
base Replace ad-hoc or locally defined power-of-2 tests 2006-02-08 10:40:43 -05:00
build Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh 2006-02-08 01:03:55 -05:00
configs Add support for multiple streams being configured with the INITPARAM 2005-11-29 18:06:15 -05:00
cpu Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh 2006-02-08 01:03:55 -05:00
dev byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions. 2006-02-03 00:16:44 -05:00
docs Many files: 2005-06-05 05:16:00 -04:00
encumbered/cpu/full Many files: 2005-06-05 05:16:00 -04:00
kern Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh 2006-02-08 01:03:55 -05:00
python Virtualize sinic 2005-11-25 13:33:36 -05:00
sim Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh 2006-02-08 01:03:55 -05:00
test Minor fix for test/genini.py. 2005-10-31 22:41:14 -05:00
util Make the M5 Emacs C style default to inserting spaces instead 2006-01-30 14:32:00 -05:00
Doxyfile Fix minor doxygen issues. 2005-06-05 08:08:29 -04:00
LICENSE Fix a few broken or inconsistently formatted copyrights 2005-06-05 05:08:37 -04:00
README More documentation for 1.1 release. 2005-10-06 13:59:05 -04:00
RELEASE_NOTES More documentation for 1.1 release. 2005-10-06 13:59:05 -04:00
SConscript A fix for SConscript so it will work with newer versions of scons 2006-02-09 13:06:47 -05:00

README 

This is release m5_1.1 of the M5 simulator.

This file contains brief "getting started" instructions.  For more
information, see http://m5.eecs.umich.edu.  If you have questions,
please send mail to m5sim-users@lists.sourceforge.net.

WHAT'S INCLUDED (AND NOT)
-------------------------

The basic source release includes these subdirectories:
 - m5: the simulator itself
 - m5-test: regression tests
 - ext: less-common external packages needed to build m5
 - alpha-system: source for Alpha console and PALcode

To run full-system simulations, you will need compiled console,
PALcode, and kernel binaries and one or more disk images.  These files
are collected in a separate archive, m5_system_1.1.tar.bz2.  This file
is included on the CD release, or you can download it separately from
Sourceforge.

M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP
Tru64 version of Unix. We are able to distribute Linux and FreeBSD
bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-dev@eecs.umich.edu.

The CD release includes a few extra goodies, such as a tar file
containing doxygen-generated HTML documentation (html-docs.tar.gz), a
set of Linux source patches (linux_m5-2.6.8.1.diff), and the scons
program needed to build M5.  If you do not have the CD, the same HTML
documentation is available online at http://m5.eecs.umich.edu/docs,
the Linux source patches are available at
http://m5.eecs.umich.edu/dist/linux_m5-2.6.8.1.diff, and the scons
program is available from http://www.scons.org.

WHAT'S NEEDED
-------------
- GCC version 3.3 or newer
- Python 2.3 or newer
- SCons 0.96.1 or newer (see http://www.scons.org)

WHAT'S RECOMMENDED
------------------
- MySQL (for statistics complex statistics storage/retrieval)
- Python-MysqlDB (for statistics analysis) 

GETTING STARTED
---------------

There are two different build targets and three optimizations levels:

Target:
-------
ALPHA_SE - Syscall emulation simulation
ALPHA_FS - Full system simulation

Optimization:
-------------
m5.debug - debug version of the code with tracing and without optimization
m5.opt   - optimized version of code with tracing
m5.fast  - optimized version of the code without tracing and asserts

Different targets are built in different subdirectories of m5/build.
Binaries with the same target but different optimization levels share
the same directory.  Note that you can build m5 in any directory you
choose;p just configure the target directory using the 'mkbuilddir'
script in m5/build.

The following steps will build and test the simulator.  The variable
"$top" refers to the top directory where you've unpacked the files,
i.e., the one containing the m5, m5-test, and ext directories.  If you
have a multiprocessor system, you should give scons a "-j N" argument (like
make) to run N jobs in parallel.

To build and test the syscall-emulation simulator:

	cd $top/m5/build
	scons ALPHA_SE/test/opt/quick

This process takes under 10 minutes on a dual 3GHz Xeon system (using
the '-j 4' option).

To build and test the full-system simulator:

1. Unpack the full-system binaries from m5_system_1.1.tar.bz2.  (See
   above for directions on obtaining this file if you don't have it.)
   This package includes disk images and kernel, palcode, and console
   binaries for Linux and FreeBSD.
2. Edit the SYSTEMDIR search path in $top/m5-test/SysPaths.py to
   include the path to your local copy of the binaries.
3. In $top/m5/build, run "scons ALPHA_FS/test/opt/quick".

This process also takes under 10 minutes on a dual 3GHz Xeon system
(again using the '-j 4' option).