Commit graph

3386 commits

Author SHA1 Message Date
Lisa Hsu
ce6c752ede update for m5 base linux. (the last changes were for the latest m5hack, i.e. with nate's stuff in it).
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout:
    update for m5 base linux.

--HG--
extra : convert_revision : c78a1748bf8a0950450c29a7b96bb8735c1bb3d2
2006-10-08 22:05:34 -04:00
Steve Reinhardt
31f3f24214 Fixes for Port proxies and proxy parameters.
--HG--
extra : convert_revision : 76b16fe2926611bd1c12c8ad7392355ad30a5138
2006-10-08 18:26:59 -07:00
Ron Dreslinski
0a3e4d56e5 Update stats for functional path fix
--HG--
extra : convert_revision : 0f38abab28e7e44f1dc748c25938185651dd1b7d
2006-10-08 21:08:27 -04:00
Ron Dreslinski
4cfddc0d77 Make sure to propogate sendFunctional calls with functional not atomic.
src/mem/cache/cache_impl.hh:
    Fix a error case by putting a panic in.
    Make sure to propogate sendFunctional calls with functional not atomic.

--HG--
extra : convert_revision : 05d03f729a40cfa3ecb68bcba172eb560b24e897
2006-10-08 20:47:50 -04:00
Ron Dreslinski
5cb1840b31 Fixes for functional path.
If the cpu needs to update any state when it gets a functional write (LSQ??)
then that code needs to be written.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    CPU's can recieve functional accesses, they need to determine if they need to do anything with them.
src/mem/bus.cc:
src/mem/bus.hh:
    Make the fuctional path do the correct tye of snoop

--HG--
extra : convert_revision : 70d09f954b907a8aa9b8137579cd2b06e02ae2ff
2006-10-08 20:30:42 -04:00
Gabe Black
2df9053bb0 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

src/mem/bus.cc:
    Hand merged. Needs to be fixed

--HG--
extra : convert_revision : df03219ccfd18431cc726a063bd29d30554944a1
2006-10-08 19:14:09 -04:00
Ron Dreslinski
e65f0cef3c Only respond if the pkt needs a response.
Fix an issue with memory handling writebacks.

src/mem/cache/base_cache.hh:
src/mem/tport.cc:
    Only respond if the pkt needs a response.
src/mem/physical.cc:
    Make physical memory respond to writebacks, set satisfied for invalidates/upgrades.

--HG--
extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
2006-10-08 19:05:48 -04:00
Ron Dreslinski
8a539a774f Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : f3067efb7f3ff30158d541dfc52de4ea8edae576
2006-10-08 18:49:30 -04:00
Ron Dreslinski
1345183a89 Move away from using the statusChange function on snoops. Clean up snooping code in general.
--HG--
extra : convert_revision : 5a57bfd7742a212047fc32e8cae0dc602fdc915c
2006-10-08 18:48:03 -04:00
Gabe Black
0c574f1069 missing else
--HG--
extra : convert_revision : 8fe0e00dc3ae70b4449a78c15dd249939e644f02
2006-10-08 18:45:21 -04:00
Gabe Black
a82f017591 bus changes
src/mem/bus.cc:
src/mem/bus.hh:
    minor fix and some formatting changes
src/python/m5/objects/Bus.py:
    changed bits to bytes

--HG--
extra : convert_revision : dcd22205604b7a2727eaf2094084c4858f3589c5
2006-10-08 18:44:49 -04:00
Steve Reinhardt
5df93cc1cd Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().
--HG--
extra : convert_revision : f22ce3221d270ecf8631d3dcaed05753accd5461
2006-10-08 14:48:24 -07:00
Steve Reinhardt
911381321b Update ref stats: ll/sc, cpu_id, new kernel (?)
--HG--
extra : convert_revision : 060cb7319c4474429917a6347a9a47f390208ec8
2006-10-08 17:07:23 -04:00
Gabe Black
63023ba4c2 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 1749397443ccb320d32f8dd23c71ed0431d30cb7
2006-10-08 14:09:13 -04:00
Gabe Black
00481d1f19 A possible implementation of a multiplexed bus.
--HG--
extra : convert_revision : 3c560eda12ffd8ca539c91024baf2770b963ede8
2006-10-08 14:08:58 -04:00
Gabe Black
34b697cd04 Add in HasData, and move the define of NUM_MEM_CMDS to a more visible location.
--HG--
extra : convert_revision : 4379efe892ca0a39363ee04009e1bbb8c8f77afa
2006-10-08 14:04:49 -04:00
Steve Reinhardt
d3fba5aa30 Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory.  *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.

src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
    and PhysicalMemory.  *No* support for caches or O3CPU.

--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
2006-10-08 10:53:24 -07:00
Steve Reinhardt
be36c808f7 Rename some vars for clarity.
--HG--
extra : convert_revision : 765283ae54d2d6b5885ea44c6c1813d4bcf18488
2006-10-08 10:43:31 -07:00
Steve Reinhardt
c2f954ac69 Allocate new thread stacks and shared mem region via Process page table
for Tru64 thread library emulation.

--HG--
extra : convert_revision : dbd307536e260e24ef79130d2aa88d84e33f03d4
2006-10-08 04:29:40 -04:00
Kevin Lim
8949d813ff Clean up configs.
configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
    Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
    Add in default FUPool.
src/python/m5/objects/O3CPU.py:
    Use defaults better.  Also set checker parameters, and fix up a config bug.

--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
2006-10-08 01:12:42 -04:00
Kevin Lim
b17421da20 Record numCycles properly.
src/cpu/simple/timing.cc:
    Record numCycles stat properly.
src/cpu/simple/timing.hh:
    Extra variable to help record numCycles stat.

--HG--
extra : convert_revision : 343311902831820264878aad41dc619999726b6b
2006-10-08 00:55:05 -04:00
Kevin Lim
d48ea81ba2 Updates to O3 CPU. It should now work in FS mode, although sampling still has a bug.
src/cpu/o3/commit_impl.hh:
    Fixes for compile and sampling.
src/cpu/o3/cpu.cc:
    Deallocate and activate threads properly.  Also hopefully fix being able to use caches while switching over.
src/cpu/o3/cpu.hh:
    Fixes for deallocating and activating threads.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit.hh:
    Handle getting back a BadAddress result from the access.
src/cpu/o3/iew_impl.hh:
    More debug output.
src/cpu/o3/lsq_unit_impl.hh:
    Fixup store conditional handling (still a bit of a hack, but works now).

    Also handle getting back a BadAddress result from the access.
src/cpu/o3/thread_context_impl.hh:
    Deallocate context now records if the context should be fully removed.

--HG--
extra : convert_revision : 55f81660602d0e25367ce1f5b0b9cfc62abe7bf9
2006-10-08 00:53:41 -04:00
Kevin Lim
c0e53b6d4c Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 0309a453c0d65579cfa022888d1a2ab4f0171a9f
2006-10-07 23:35:32 -04:00
Ali Saidi
abc27ae691 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : acab791328d16daace6dfbdc667067ddc68fb6ca
2006-10-07 14:49:10 -04:00
Kevin Lim
3afc69df77 Merge ktlim@zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : b013b35f5c2264712eb51bef5623b208eb6128f9
2006-10-07 13:41:49 -04:00
Kevin Lim
fe762278e7 Updates to bring MemTest closer to working with newmem. Ron still needs to do the initial setup and configuration for it to work properly.
src/SConscript:
    Include MemTest for now.  It's not complete but it compiles so it shouldn't mess anything else up.

--HG--
extra : convert_revision : 15a610c855b677fdced817850c92e4c911cf6d1c
2006-10-07 13:37:22 -04:00
Ron Dreslinski
413a5379b8 Update stats for change in functional path in cache
--HG--
extra : convert_revision : 5abc964ca95b80522266c5c1bc5e661d41f2798a
2006-10-07 12:58:37 -04:00
Ron Dreslinski
467c17fbd9 Fix a missing pointer
--HG--
extra : convert_revision : 2056b530d48fd004ab700f09e58f44adae3ea0e9
2006-10-07 12:55:37 -04:00
Ron Dreslinski
fdaed2c7ae No need to keep trying to request the data bus if we are already waiting.
--HG--
extra : convert_revision : dbaad52ed8d0841dc9224661e3df0d8ef4989aa3
2006-10-07 12:20:29 -04:00
Ron Dreslinski
df3014a726 Add mechanism for caches to handle failure of the fast path on responses.
For now, responses have priority over requests (may want to revist this).

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
    Add mechanism for caches to handle failure of the fast path on responses.

--HG--
extra : convert_revision : 01524c727d1bb300cc21bdc989eb862ec8bf0b7a
2006-10-07 12:02:59 -04:00
Ron Dreslinski
2c336f0a1f Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 10cdbc57c8fa1cae755e0a224bc74ea8f3782c75
2006-10-07 11:37:18 -04:00
Ron Dreslinski
178d114fa5 Fix infinite writebacks bug in cache.
src/mem/cache/cache_impl.hh:
    Make sure to pop the list.  Fixes infinite writeback bug.
src/mem/cache/miss/mshr_queue.cc:
    Add an assert as sanity check in case .full() stops working again.

--HG--
extra : convert_revision : d847e49a397eeb0b7c5ac060fcfc3eaeac921311
2006-10-07 11:36:55 -04:00
Kevin Lim
984579a6ad Update refs.
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
    Update refs. (Korey's initial push didn't use the default O3-timing config?)

--HG--
extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
2006-10-07 11:32:10 -04:00
Ali Saidi
c60c61b19e Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 326605820dce7641058eb0cdc0ddb2cc9602f67e
2006-10-06 21:46:04 -04:00
Ali Saidi
b7832555d5 system.cc:
Make new_page() check for an out of memory condition

src/sim/system.cc:
    Make new_page() check for an out of memory condition

--HG--
extra : convert_revision : daee82788464fca186eb24285b5f43c9fabc25b3
2006-10-06 21:45:34 -04:00
Gabe Black
862825f997 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 8b5536f276527adcc27e11e790262232aeb61b13
2006-10-06 17:10:13 -04:00
Ron Dreslinski
c42a7bc4f6 Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 2f1bbe84c92879fd1bfa579adc62a367ece1cddd
2006-10-06 09:28:16 -04:00
Ron Dreslinski
dfdb683fb9 Another thread number removed
--HG--
extra : convert_revision : 4cfb83b8162745d686e8697f29f74f37b1a71525
2006-10-06 09:27:59 -04:00
Ron Dreslinski
1b6653b6f7 Remove threadnum from cache everywhere for now
Fix so that blocking for the same reason doesn't fail.  I.E. multiple writebacks want to set the blocked flag.

src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
    Remove threadnum from cache everywhere for now

--HG--
extra : convert_revision : 7890712147655280b4f1439d486feafbd5b18b2b
2006-10-06 09:15:53 -04:00
Korey Sewell
48e89a9d1e Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/m5-clean

--HG--
extra : convert_revision : 25200efe03b7cf9b3c546c939be74210f65a196a
2006-10-06 04:24:02 -04:00
Korey Sewell
84dac99e2e add SMT hello world test - 2 threads
--HG--
extra : convert_revision : 54cb19d1325295895b6f0b992499bbb0216b45df
2006-10-06 04:23:27 -04:00
Lisa Hsu
fb3a30f87c checkpoint recovery was screwed up because a new section was created in the middle of another section and messed up unserializing.
--HG--
extra : convert_revision : 7af15fdc9e8d203b26840a2eb5fef511b6a2b21d
2006-10-06 01:29:50 -04:00
Lisa Hsu
9c901225f8 there are two main thrusts of this changeset.
1) return the periodicity of checkpoints back into the code (i.e. make m5 checkpoint n m meaningful again).
2) to do this, i had to much around with being able to repeatedly schedule and SimLoopExitEvent, which led to changes in how exit simloop events are handled to make this easier.

src/arch/alpha/isa/decoder.isa:
src/mem/cache/cache_impl.hh:
    modify arg. order for new calling convention of exitSimLoop.
src/cpu/base.cc:
src/sim/main.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
    now, instead of creating a new SimLoopExitEvent, call a wrapper schedExitSimLoop which handles all the default args.
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_exit.hh:
    add the periodicity of checkpointing back into the code.

    to facilitate this, there are now two wrappers (instead of just overloading exitSimLoop).  exitSimLoop is only for exiting NOW (i.e. at curTick), while schedExitSimLoop schedules and exit event for the future.

--HG--
extra : convert_revision : c61f4bf05517172edd2c83368fd10bb0f0678029
2006-10-06 01:27:02 -04:00
Lisa Hsu
54cf456fd1 add an option for defining a directory in which to place all your checkpoints. if none, default is cwd.
--HG--
extra : convert_revision : 23a602c2d800c922346c9743cc0c583d178a0ee7
2006-10-06 00:42:39 -04:00
Lisa Hsu
7e63d67f08 Merge zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/z/hsul/newmem

--HG--
extra : convert_revision : ecf61b323a93c9192450388c8812c26b919d06cb
2006-10-06 00:39:49 -04:00
Lisa Hsu
230fb85a8a update full system references for newest disk image from linux-dist.
--HG--
extra : convert_revision : c1232dafff0d92d8041af1b9de1dc8c55ee50f40
2006-10-06 00:39:21 -04:00
Nathan Binkert
dfa065ad16 Merge zizzer.eecs.umich.edu:/bk/newmem
into  iceaxe.:/Volumes/work/research/m5/incoming

--HG--
extra : convert_revision : b4d6a36ee07d858829369027127e00a2aec097fd
2006-10-05 21:16:42 -07:00
Nathan Binkert
8dcca68234 remove traces of binning
--HG--
extra : convert_revision : b33cc67cfde04c9af6f50cbef538104e1298bedc
2006-10-05 21:14:43 -07:00
Ron Dreslinski
212c5aefb5 Fixes for functional accesses to use the snoop path.
And small other tweaks to snooping coherence.

src/mem/cache/base_cache.hh:
    Make timing response at the time of send.
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
    Update probe interface to be bi-directional for functional accesses
src/mem/packet.hh:
    Add the function to create an atomic response to a given request

--HG--
extra : convert_revision : 04075a117cf30a7df16e6d3ce485543cc77d4ca6
2006-10-05 23:28:03 -04:00
Ron Dreslinski
45f881a4ce First pass at snooping stuff that compiles and doesn't break.
Still need:
-Handle NACK's on the recieve side
-Distinguish top level caches
-Handle repsonses from caches failing the fast path
-Handle BusError and propogate it
-Fix the invalidate packet associated with snooping in the cache

src/mem/bus.cc:
    Make sure to snoop on functional accesses
src/mem/cache/base_cache.cc:
    Wait to make a request into a response until it is ready to be issued
src/mem/cache/base_cache.hh:
    Support range changes for snoops
    Set up snoop responses for cache->cache transfers
src/mem/cache/cache_impl.hh:
    Only access the cache if it wasn't satisfied by cache->cache transfer
    Handle snoop phases (detect block, then snoop)
    Fix functional access to work properly (still need to fix snoop path for functional accesses)

--HG--
extra : convert_revision : 4c25f11d7a996c1f56f4f7b55dde87a344e5fdf8
2006-10-05 21:10:03 -04:00