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135 commits

Author SHA1 Message Date
Nathan Binkert 90820ddf02 config: fix assertion for x86 in FSConfig.py 2010-04-18 21:33:59 -07:00
Brad Beckmann 898f1fc4a4 ruby: Reorganized Ruby topology and protocol files 
--HG--
rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/protocols/MESI_CMP_directory.py
rename : configs/ruby/MI_example.py => configs/ruby/protocols/MI_example.py
rename : configs/ruby/MOESI_CMP_directory.py => configs/ruby/protocols/MOESI_CMP_directory.py
rename : configs/ruby/MOESI_CMP_token.py => configs/ruby/protocols/MOESI_CMP_token.py
rename : configs/ruby/MOESI_hammer.py => configs/ruby/protocols/MOESI_hammer.py
rename : configs/ruby/networks/MeshDirCorners.py => src/mem/ruby/network/topologies/MeshDirCorners.py
 2010-03-21 21:22:22 -07:00
Brad Beckmann 4f044605e8 ruby: Adds configurable bit selection for numa mapping 2010-03-21 21:22:21 -07:00
Brad Beckmann 92cfd1cac7 ruby: Ruby support for sparse memory 
The patch includes direct support for the MI example protocol.
 2010-03-21 21:22:21 -07:00
Brad Beckmann d8e1e5abd0 ruby: fixed how ruby_fs creates phsyical memory 
Now ruby_fs creates physical memory of the right size.
 2010-03-21 21:22:20 -07:00
Lisa Hsu a70f70ccbf configs: pull out cache configuration code from se.py and fs.py. 
Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.
 2010-02-25 10:13:40 -08:00
Brad Beckmann 8dd45674ae ruby: Converted Garnet to M5 configuration 2010-01-29 20:29:32 -08:00
Brad Beckmann 6c867f8263 ruby: Added a mesh topology 2010-01-29 20:29:27 -08:00
Brad Beckmann d77a9df3c1 ruby: MOESI_CMP_token updates to use the new config system 2010-01-29 20:29:25 -08:00
Brad Beckmann ce2d13195b ruby: FS support using the new configuration system 2010-01-29 20:29:21 -08:00
Brad Beckmann dc758641c9 ruby: reorganized ruby python configuration 
Reorganized ruby python configuration so that protocol and ruby memory system
configuration code can be shared by multiple front-end configuration files
(i.e. memory tester, full system, and hopefully the regression tester).  This
code works for memory tester, but have not tested fs mode.
 2010-01-29 20:29:20 -08:00
Gabe Black 93d89b288f X86: Record the memory mode when building an X86 system. 2009-12-19 01:49:34 -08:00
Brad Beckmann 70a261c0ae m5: Added option to take a checkpoint at the end of simulation 2009-11-18 13:55:58 -08:00
Brad Beckmann b8c413e993 m5: Moved profile option since Simulation depends on it. 2009-11-18 13:55:58 -08:00
Brad Beckmann 3cf24f9716 ruby: Support for merging ALPHA_FS and ruby 
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers.  Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
 2009-11-18 13:55:58 -08:00
Nathan Binkert 9a8cb7db7e python: Move more code into m5.util allow SCons to use that code. 
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.

--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
 2009-09-22 15:24:16 -07:00
Korey Sewell 7858a8e68f configs: add maxinsts option on command line 
-option to allow threads to run to a max_inst_any_thread which is more useful/quicker in a lot of
cases then always having to figure out what tick to run your simulation to.
 2009-09-16 09:45:30 -04:00
Korey Sewell 9f90291c54 cpus: fix cpu progress event 
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
 2009-05-05 02:39:05 -04:00
Gabe Black 8d84f81e70 X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment. 2009-04-26 02:04:32 -07:00
Steve Reinhardt 6629d9b2bc mem: use single BadAddr responder per system. 
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond.  Now there is just one on
the main memory bus.  The default bus responder on all other buses
is now the downstream cache's cpu_side port.  Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
 2008-07-16 11:10:33 -07:00
Steve Reinhardt 97b6947eb7 Minor tweaks for future Ruby compatibility. 2009-04-21 08:17:36 -07:00
Gabe Black b8333a5155 X86: Actually put the PCI INTA entry into the MP tables. 2009-04-19 04:15:18 -07:00
Gabe Black 25e223c30f X86: Make E820 report nice, round (and correct) numbers. 2009-04-19 04:14:48 -07:00
Gabe Black 06d25dcd26 X86: Automatically make the IO APIC in an N CPU system have id N+1. 2009-04-19 02:39:19 -07:00
Steve Reinhardt 9b66e82897 configs: Allow M5_CPU2000 env var to set CPU2K binary path. 
It would be nice to have a more comprehensive mechanism
but this is a big improvement over manually editing the script.
 2009-04-15 12:52:31 -07:00
Gabe Black eafdf00eb3 X86: Add IRQ4 to the Intel MP tables. 2009-02-25 10:19:06 -08:00
Korey Sewell cf4a00ca41 Configs: Add support for the InOrder CPU model 2009-02-10 15:49:29 -08:00
Gabe Black 1c5b9773bd X86: Find the natural lpj for this configuration. 2009-02-01 00:29:07 -08:00
Gabe Black a5ed1590bd X86: Add a root device to the kernel command line. 2009-02-01 00:27:49 -08:00
Gabe Black 70cd5bfce5 X86: Configure the first PCI interrupt. 2009-02-01 00:26:10 -08:00
Gabe Black 18f6c18323 X86: Hook in a hard drive image. 2009-02-01 00:24:26 -08:00
Gabe Black 01679bb416 X86: Take out the IDE noprobe kernel arguments. 2009-02-01 00:20:44 -08:00
Gabe Black bb7ad80bbe X86: Plug in an IDE controller. 2009-02-01 00:00:03 -08:00
Gabe Black d08b8e2b82 X86: Add some interrupt info to the intel MP tables. 2009-01-31 23:43:09 -08:00
Ali Saidi f4291aac25 Errors: Print a URL with a hash of the format string to find more information about an error. 2009-01-30 20:04:15 -05:00
Gabe Black 7b7a92d3f4 X86: Prevent Linux for probing for non-existant IDE controllers. 2009-01-25 20:36:24 -08:00
Gabe Black ff29e00112 X86: Add entries for the IO APIC to the MP table. 2008-10-11 16:12:34 -07:00
Gabe Black 526933e5d0 X86: Add an Intel MP table to the simulation. 2008-10-11 15:14:37 -07:00
Gabe Black 3af428606a X86: Rename the PC device to Pc. 
--HG--
rename : src/dev/x86/PC.py => src/dev/x86/Pc.py
 2008-10-11 02:23:40 -07:00
Gabe Black ec0fb05d64 X86: Turn SMBios structures into simobjects. 2008-10-10 03:50:51 -07:00
Gabe Black b4dab225fd X86: Split makeLinuxX86System into makeLinuxX86System and makeX86System. 2008-10-10 03:50:30 -07:00
Ali Saidi 3a3e356f4e style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
Nathan Binkert 00df9016fe Rename SimConsole to Terminal since it makes more sense 
--HG--
rename : src/dev/SimConsole.py => src/dev/Terminal.py
rename : src/dev/simconsole.cc => src/dev/terminal.cc
rename : src/dev/simconsole.hh => src/dev/terminal.hh
 2008-06-17 20:29:06 -07:00
Gabe Black bceaa257a3 X86: Make the e820 table manually or automatically configurable from python. 2008-06-12 00:58:36 -04:00
Gabe Black 561a541797 X86: Force the kernel to use a certain loops per jiffy instead of calculating it. 2008-06-12 00:46:16 -04:00
Gabe Black f6a97752b0 X86: Make the amount of system memory match the hardcoded e820 info. 2008-06-12 00:45:11 -04:00
Gabe Black 633c585bfa X86: Make the regular console use the serial port as well. 2008-06-12 00:45:01 -04:00
Gabe Black b0c52885ce X86: Change the Opteron platform to be the PC platform. 
--HG--
extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37
 2008-03-25 02:06:53 -04:00
Ali Saidi 969688154d Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint doesn't exist 
--HG--
extra : convert_revision : c156c49668815755c4c788f807e8eba32151aa24
 2008-03-15 22:20:09 -04:00
Lisa Hsu 02a56d8d01 Error out if -s is used without --caches (instead of saying you must specify a 
CPU).

--HG--
extra : convert_revision : a3b2bfbe7e037146ac08dd08834bf255da692506
 2008-02-29 01:49:36 -05:00