Commit graph

1742 commits

Author SHA1 Message Date
Gabe Black
903fb8c73d ARM: Create a new type of load uop that restores spsr into cpsr. 2009-11-15 00:15:42 -08:00
Gabe Black
b41725f723 ARM: Check in the actual change from the last commit.
The last commit was somehow empty. This was what was supposed to go in it.
2009-11-14 21:03:10 -08:00
Gabe Black
c4042985d7 ARM: Fix up the implmentation of the msr instruction. 2009-11-14 19:22:30 -08:00
Gabe Black
e2ab64543b ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits. 2009-11-14 19:22:30 -08:00
Gabe Black
425ebf6bd7 ARM: Add a bitfield to indicate if an immediate should be used. 2009-11-14 19:22:30 -08:00
Gabe Black
e543f16247 ARM: Write some functions to write to the CPSR and SPSR for instructions. 2009-11-14 19:22:30 -08:00
Gabe Black
812e390693 ARM: Fix up the implmentation of the mrs instruction. 2009-11-14 19:22:29 -08:00
Gabe Black
1df0025e28 ARM: More accurately describe the effects of using the control operands. 2009-11-14 19:22:29 -08:00
Gabe Black
50b9149c75 ARM: Hook up the moded versions of the SPSR.
These registers can be accessed directly, or through MISCREG_SPSR which will
act as whichever SPSR is appropriate for the current mode.
2009-11-14 19:22:29 -08:00
Ali Saidi
48bc573f5f ARM: Move around decoder to properly decode CP15 2009-11-14 11:25:00 -06:00
Vince Weaver
8f6744c19c X86: add ULL to 1's being shifted in 64-bit values
Some of the micro-ops weren't casting 1 to ULL before shifting,
which can cause problems.  On the perl makerand input this
caused some values to be negative that shouldn't have been.

The casts are done as ULL(1) instead of 1ULL to match others
in the m5 code base.
2009-11-11 17:49:09 -05:00
Gabe Black
5524af83ef ARM: Fix some bugs in the ISA desc and fill out some instructions. 2009-11-10 23:44:05 -08:00
Gabe Black
850eb54a7c Merge with the head. 2009-11-10 21:12:53 -08:00
Gabe Black
b8120f6c38 Mem: Eliminate the NO_FAULT request flag. 2009-11-10 21:10:18 -08:00
Gabe Black
2e28da5583 ARM: Implement fault classes.
Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
2009-11-10 20:34:38 -08:00
Gabe Black
4779020e13 ARM: Fix the integer register indexes.
The PC indexes in the various register sets was defined in the section for
unaliased registers which was throwing off the indexing. This moves those
where they belong. Also, to make detecting accesses to the PC easier and
because it's in the same place in all modes, the intRegForceUser function
now passes it through as index 15.
2009-11-10 20:19:55 -08:00
Vince Weaver
53e27c0277 X86: Fix bugs in movd implementation.
Unfortunately my implementation of the movd instruction had two bugs.

In one case, when moving a 32-bit value into an xmm register, the
lower half of the xmm register was not zero extended.

The other case is that xmm was used instead of xmmlm as the source
for a register move.  My test case didn't notice this at first
as it moved xmm0 to eax, which both have the same register
number.
2009-11-10 11:29:30 -05:00
Vince Weaver
e81cc233a6 X86: Remove double-cast in Cvtf2i micro-op
This double cast led to rounding errors which caused
some benchmarks to get the wrong values, most notably lucas
which failed spectacularly due to CVTTSD2SI returning an
off-by-one value.  equake was also broken.
2009-11-10 11:18:23 -05:00
Gabe Black
bbbfdee2ed X86: Don't panic on faults on prefetches in SE mode. 2009-11-08 22:49:58 -08:00
Gabe Black
44e912c6bd X86: Explain what really didn't work with unmapped addresses in SE mode. 2009-11-08 22:49:57 -08:00
Gabe Black
53086dfefe X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE. 2009-11-08 22:49:57 -08:00
Nathan Binkert
b1a1f9aec8 automerge 2009-11-08 20:15:54 -08:00
Gabe Black
8a4af3668d ARM: Support forcing load/store multiple to use user registers. 2009-11-08 15:49:03 -08:00
Gabe Black
bb903b6514 ARM: Simplify the load/store multiple generation code.
Specifically, get rid of the big switch statement so more cases can be
handled. Enumerating all the possible settings doesn't scale well. Also do
some minor style clean up.
2009-11-08 15:16:59 -08:00
Nathan Binkert
708faa7677 compile: wrap 64bit numbers with ULL() so 32bit compiles work
In the isa_parser, we need to check case statements.
2009-11-08 13:31:59 -08:00
Gabe Black
48525f581c ARM: Split the condition codes out of the CPSR.
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
2009-11-08 02:08:40 -08:00
Gabe Black
d188821d37 ARM: Add in more bits for the mon mode. 2009-11-08 02:01:02 -08:00
Gabe Black
3a3e846151 ARM: Get rid of NumInternalProcRegs.
That constant is a carry over from Alpha and doesn't do anything in ARM.
2009-11-08 02:00:55 -08:00
Gabe Black
78bd8fe44f ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR. 2009-11-08 01:59:20 -08:00
Gabe Black
f63c260d89 ARM: Get rid of the Raddr operand. 2009-11-08 01:57:34 -08:00
Gabe Black
43e9209c21 ARM: Initialize processes in user mode.
I accidentally left in a change to test using int registers in system mode.
This change reverts that.
2009-11-08 00:54:32 -08:00
Gabe Black
a2b76516c4 ARM: Implement the shadow registers using register flattening. 2009-11-08 00:07:49 -08:00
Gabe Black
4a454c4f47 ARM: Set up an intregs.hh for ARM.
Add constants for all the modes and registers, maps for aliasing, functions
that use the maps and range check, and use a named constant instead of a magic
number for the microcode register.
2009-11-08 00:07:35 -08:00
Gabe Black
18b21c1eca ARM: Get rid of some unneeded register indexes. 2009-11-07 22:34:33 -08:00
Vince Weaver
5cf2e7ccf0 X86: Fix problem with movhps instruction
This problem is like the one fixed with movhpd a few weeks ago.
A +8 displacement is used to access memory when there should
be none.

This fix is needed for the perlbmk spec2k benchmark to run.
2009-11-04 13:22:15 -05:00
Nathan Binkert
2c5fe6f95e build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
Vince Weaver
a1042db290 X86: Enable x86_64 vsyscall support
64-bit vsyscall is different than 32-bit.
There are only two syscalls, time and gettimeofday.
On a real system, there is complicated code that implements these
without entering the kernel.  That would be complicated to implement in m5.
Instead we just place code that calls the regular syscalls (this is how
tools such as valgrind handle this case).

This is needed for the perlbmk spec2k benchmark.
2009-11-04 00:47:12 -05:00
Vince Weaver
9b0a747dd4 X86: Hook up time syscall on X86
This has been tested and verified that it works.
2009-11-04 00:19:15 -05:00
Vince Weaver
a12557439b X86: Add support for x86 psrldq and pslldq instructions
These are complicated instructions and the micro-code might be suboptimal.

This has been tested with some small sample programs (attached)

The psrldq instruction is needed by various spec2k programs.
2009-10-30 12:49:37 -04:00
Vince Weaver
5873ec2238 X86: Implement movd_Vo_Edp on X86
This patch implements the movd_Vo_Edp series of instructions.

It addresses various concerns by Gabe Black about which file the
instruction belonged in, as well as supporting REX prefixed
instructions properly.

This instruction is needed for some of the spec2k benchmarks, most
notably bzip2.
2009-10-30 15:52:33 -04:00
Vince Weaver
b2067840a6 X86: Implement the X86 sse2 haddpd instruction
This patch implements the haddpd instruction.

It fixes the problem in the previous version (pointed out by Gabe Black)
where an incorrect result would happen if you issue the instruction
with the same argument twice, i.e. "haddpd %xmm0,%xmm0"

This instruction is used by many spec2k benchmarks.
2009-10-30 14:19:06 -04:00
Vince Weaver
cf269025f9 X86: Hookup truncate/ftruncate syscalls on X86
This patch hooks up the truncate, ftruncate, truncate64 and ftruncate64
system calls on 32-bit and 64-bit X86.

These have been tested on both architectures.

ftruncate/ftruncate64 is needed for the f90 spec2k benchmarks.
2009-10-30 12:51:13 -04:00
Gabe Black
3f722b991f Syscalls: Make system calls access arguments like a stack, not an array.
When accessing arguments for a syscall, the position of an argument depends on
the policies of the ISA, how much space preceding arguments took up, and the
"alignment" of the index for this particular argument into the number of
possible storate locations. This change adjusts getSyscallArg to take its
index parameter by reference instead of value and to adjust it to point to the
possible location of the next argument on the stack, basically just after the
current one. This way, the rules for the new argument can be applied locally
without knowing about other arguments since those have already been taken into
account implicitly.

All system calls have also been changed to reflect the new interface. In a
number of cases this made the implementation clearer since it encourages
arguments to be collected in one place in order and then used as necessary
later, as opposed to scattering them throughout the function or using them in
place in long expressions. It also discourages using getSyscallArg over and
over to retrieve the same value when a temporary would do the job.
2009-10-30 00:44:55 -07:00
Gabe Black
f9624e49f6 X86: Replace "DISPLACEMENT" with disp in movhpd. 2009-10-27 23:50:25 -07:00
Vince Weaver
87b97f28bd Fix problem with the x86 sse movhpd instruction.
The movhpd instruction was writing to the wrong memory offset.
2009-10-27 14:11:06 -04:00
Vince Weaver
14691148cd Implement X86 sse2 movdqu and movdqa instructions
The movdqa instruction should enforce 16-byte alignment.
This implementation does not do that.

These instructions are needed for most of x86_64 spec2k to run.
2009-10-21 13:40:43 -04:00
Vince Weaver
5b6f707a00 hook up stat syscall on 64-bit x86_SE 2009-10-20 16:48:00 -04:00
Vince Weaver
2b473cb099 hook up stat64 syscall on 32-bit X86_SE 2009-10-20 14:44:51 -04:00
Vince Weaver
776f9405fa Fix stat64 structure on 32-bit X86_SE
The st_size entry was in the wrong place
 (see linux-2.6.29/arch/x86/include/asm/stat.h )

Also, the packed attribute is needed when compiling on a
64-bit machine, otherwise gcc adds extra padding that
break the layout of the structure.
2009-10-20 15:15:37 -04:00
Timothy M. Jones
835a55e7f3 POWER: Add support for the Power ISA
This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
2009-10-27 09:24:39 -07:00