Commit graph

11739 commits

Author SHA1 Message Date
Andreas Hansson
7dc5034ff2 arm: Fix heap overflow issue in Neon64Load operation
This patch fixes an issue identified by ASAN where the Neon64Load
operation assumes the packet always contains 16 bytes.

Change-Id: If24a7e461d60cb80970dfbe61d923d7d56926698
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-26 11:56:24 +01:00
Andreas Hansson
4a3e2156ac arm, dev: Remove superfluous loop increment in flash device
As identified by clang-3.8, there was a superfluous loop increment in
the flash device which is now removed.

Change-Id: If46a1c4f72d3d4c9f219124030894ca433c790af
Reviewed-by: Rene De Jong <rene.dejong@arm.com>
2016-05-26 11:56:24 +01:00
Nikos Nikoleris
a69a0f33cb mem: fix headers include order in the cache related classes
Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26 11:56:24 +01:00
Nikos Nikoleris
f9d62b63e1 mem: remove redudant check whether the cache forwards snoops
Change-Id: I57b56771086e1e2f512977fb7248d93c171ab925
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26 11:56:24 +01:00
Nikos Nikoleris
d68f3577d6 mem: change NULL to nullptr in the cache related classes
Change-Id: I5042410be54935650b7d05c84d8d9efbfcc06e70
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26 11:56:24 +01:00
Nikos Nikoleris
90bf50b4c7 mem: fix the line length in the cache related classes
Change-Id: I6d1feb164a958dde0da87a1cd2698096112c4a82
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26 11:56:24 +01:00
Andreas Sandberg
f385adc8af tests: Add test infrastructure as a Python module
Implement gem5's test infrastructure as a Python module and a run
script that can be used without scons. The new implementation has
several features that were lacking from the previous test
infrastructure such as support for multiple output formats, automatic
runtime tracking, and better support for being run in a cluster
environment.

Tests consist of one or more steps (TestUnit). Units are run in two
stages, the first a run stage and then a verify stage. Units in the
verify stage are automatically skipped if any unit run stage wasn't
run. The library currently contains TestUnit implementations that run
gem5, diff stat files, and diff output files.

Existing tests are implemented by the ClassicTest class and "just
work". New tests can that don't rely on the old "run gem5 once and
diff output" strategy can be implemented by subclassing the Test base
class or ClassicTest.

Test results can be output in multiple formats. The module currently
supports JUnit, text (short and verbose), and Python's pickle
format. JUnit output allows CI systems to automatically get more
information about test failures. The pickled output contains all state
necessary to reconstruct a tests results object and is mainly intended
for the build system and CI systems.

Since many JUnit parsers parsers assume that test suite names look
like Java package names. We currently output path-like names with
slashes separating components. Test names are translated according to
these rules:

  * '.' -> '-"
  * '/' -> '.'

The test tool, tests.py, supports the following features:

  * Test listing. Example: ./tests.py list arm/quick

  * Running tests. Example:
    ./tests.py run -o output.pickle --format pickle \
        ../build/ARM/gem5.opt \
        quick/se/00.hello/arm/linux/simple-timing

  * Displaying pickled results. Example:
    ./tests.py show --format summary *.pickle

Change-Id: I527164bd791237aacfc65e7d7c0b67b695c5d17c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Joel Hestness <jthestness@gmail.com>
2016-05-26 11:56:24 +01:00
Bjoern A. Zeeb
7fc668fae9 config, x86: Properly space pad the X86IntelMPBus Entry descriptions
According to the Intel Multi Processor Specification rev 1.4 (-006) (*),
section 4.3.2 Bus Entries, Bus type strings are >>6-character ASCII
(blank-filled) strings<<.
This patch properly pads the entries with the missing spaces at the end.

(*) http://www.intel.com/design/pentium/datashts/24201606.pdf

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19 15:19:35 -05:00
Bjoern A. Zeeb
a6b00c07f6 arm,dev: PL011 UART_FR read status enhancement
Given we do not simulate a FIFO currently there are only two states
we can be in upon read: empty or full.  Properly signal the latter.

Add and sort constants for states in the header file.

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19 15:19:35 -05:00
Bjoern A. Zeeb
5fa6b68981 x86, dev: properly space the APIC registers
Registers are 0x10 and not 0x8 apart.  The latter leads to invalid
calculations of index in array which in turn means that we will not
find the interrupt we were looking (been notified) for in the OS.

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19 15:19:35 -05:00
Bjoern A. Zeeb
ce610dcab1 dev, virtio: properly set PCI address space to use IOREG
VirtIO spec < 1.0 demands IOREG to be used on PCI and not memory mapped.
Set the correct bit on the PCI address accordingly.

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19 15:19:34 -05:00
Tony Gutierrez
7dad4377ec gpu-compute: fix bug in GPUDynInst::isScalarRegister() 2016-05-16 15:36:24 -04:00
Andreas Sandberg
5131a768c3 scons: Rewrite git style hook installer
The SCons script currently assumes that .git is a proper directory
with all git meta data. This isn't the case if the working directory
was checked out using git worktrees. In such case .git is a file with
meta data telling git where the repository data is stored.

This changeset updates changes the SConstruct file to rely on git
rev-parse to get the real git directory.

Change-Id: I3d0475eabc12e868193797067a88e540a9b6e927
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-09 11:32:11 +01:00
Andreas Sandberg
8b412fcfd6 tests: Enable test running outside of gem5's source tree
The learning gem5 scripts currently assumes that the current working
directory is the root of gem5's source tree. This isn't necessarily
the case when running the tests using gem5's new test runner.

Change-Id: Ief569bbe77b1b3e2b0fb0e6c575fb0705bbba9b3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-09 11:32:07 +01:00
Steve Reinhardt
2ae8b365c1 tests: update EIO ref stats for removed cache stats
Complaints about changes in EIO tests were due to reference files
that still have removed cache stats from cset 11454:e55afadc4e19.
2016-05-07 14:43:06 -04:00
Tony Gutierrez
bb83fa2051 gpu-compute: fix spacing in GPUDynInst ctor 2016-05-06 17:00:54 -04:00
Tony Gutierrez
4f3139e696 gpu-compute: fix uninitialized member bug in GPUDynInst
the n_reg field in the GPUDynInst is not currently set in the constructor.
if it is not set externally, there are assertion failures that may occur
if the random value it gets is just right. here we set it to 0 by default.
2016-05-06 16:44:38 -04:00
Andreas Sandberg
84cfa10b15 dev, arm: Update GIC to use GICv2 register naming
The GICv2 has a new and slightly more consistent register
naming. Update gem5's GIC register names to match the new
documentation.

Change-Id: I8ef114eee8a95bf0b88b37c18a18e137be78675a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-06 15:52:34 +01:00
Andreas Sandberg
a46f77e695 arm: Update dts to work with the new HDLCD driver
The dts files in system/arm/dt currently assume that an (unreleased)
gem5-specific virtual encoder is used as a remote endpoint for the
HDLCD. This driver won't be released as a more general virtual encoder
is about to be posted on the Linux DRI devel list and this encoder has
now been merged with gem5's kernel tree. This changeset updates gem5's
dts files to use that encoder.

Change-Id: Ic1a1be728efd31603752fdfba005b6dbdea42e7e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Rene De Jong <rene.dejong@arm.com>
2016-05-06 15:51:45 +01:00
Curtis Dunham
fa5fda90c0 scons: emit correct message before installing git hook
Change-Id: Ied2e018a9a1b6db446edbaac871ac4efd795ec36
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28 15:20:03 +01:00
Curtis Dunham
3f24000d46 style: ignore test data in style checks
Change-Id: If797eaf3842b5c1604942bb60f091800ee814a2a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28 15:19:58 +01:00
Curtis Dunham
64dccbbf1b style: respect ignores for git commit
Previously it ignored the ignores for git but not Mercurial.

Change-Id: I178fe879ebd268e863063eb9e30ec87e8ac8faec
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28 15:18:52 +01:00
Curtis Dunham
8be5717a02 style: improve compatibility with old git versions
Older versions of git need the '=' to connect --diff-filter to
its argument.

Change-Id: Ic62057567db061684be88a7c2d80a6a5d4c11dcf
2016-04-28 15:17:50 +01:00
Andreas Sandberg
f8c6ff1d1b style: Don't include diff context in git style hook
The git style hook currently includes a few lines of diff context when
determining changed regions. This is undesirable as this triggers
false positives when modifying existing files with a lot of style
violations. This change sets the amount of context to 0, which is the
default value when requesting staged regions from the git helper.

Change-Id: Ibe03123e329ea0241281e104183a68d6c495b190
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-04-28 15:17:28 +01:00
Andreas Sandberg
b80f568bcf tests: Remove stale reference output files
Remove test reference files that are not generated any more:

    * chair.cook.ppm: This file should be generated by eon and not
      mcf, so it shouldn't be included as an output from mcf.

    * system.pc.terminal: The terminal device has been renamed so this
      file is no longer generated.

Change-Id: I3962efe1ff25479ca276115f7564eccb5fac8cf9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28 15:16:52 +01:00
Andreas Sandberg
53f58b5fc1 arm: Remove BreakPCEvent on guest kernel panic
The LinuxArmSystem class normally provides support for panicing gem5
if the simulated kernel panics. When this is turned off (default),
gem5 uses a BreakPCEvent to provide a debugger hook into the simulator
when the kernel crashes. This hook unconditionally kills gem5 with a
SIGTRAP unless gem5 is compiled in fast mode. This is undesirable
since the panic_on_panic param already provides similar functionality.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27 15:34:58 +01:00
Andreas Sandberg
f1575fdc4a kvm, arm: Make GIC interrupt lines configurable
Add support for overriding the number of interrupt lines in the ARM
KvmGic.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27 15:34:48 +01:00
Andreas Sandberg
d5e7892350 kvm, arm: Refactor KVM GIC device
Factor out the kernel device wrapper from the KvmGIC and put it in a
separate class. This will simplify a future kernel/gem5 hybrid GIC.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27 15:34:31 +01:00
Andreas Sandberg
6d74892b38 dev: Fix incorrect terminal backlog handling
The Terminal device currently uses the peek functionality in gem5's
circular buffer implementation to send existing buffered content on
the terminal when a new client attaches. This functionallity is
however not implemented correctly and re-sends the same block multiple
time.

Add the required functionality to peek with an offset into the
circular buffer and change the Terminal::accept() implementation to
send the buffered contents.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27 15:33:58 +01:00
Matthew Poremba
67e93a5846 ruby: Rename pkt to m_pkt so it may be accessed via SLICC
Allow usage of packet class in ruby for convenience purposes. This may be
used to access members of the packet/request class (e.g., via helper
functions) and/or push protocol specific information to the packets
SenderState without needing to modify SLICC types and protocols in multiple
locations.
2016-04-26 12:07:51 -04:00
Andreas Hansson
8845aae4da tests: Add a basic memcheck regression
This patch adds a simple regression that calls the existing
memcheck.py script.

--HG--
rename : tests/configs/learning-gem5-p1-simple.py => tests/configs/memcheck.py
rename : tests/quick/se/70.tgen/test.py => tests/quick/se/51.memcheck/test.py
2016-04-25 03:46:12 -04:00
Jason Power
bf7e27fe45 tests: Update learning gem5 tests scripts with copyright 2016-04-21 17:25:31 -05:00
Andreas Hansson
b006ad26d4 stats: Update stats to reflect cache changes
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
2016-04-21 04:48:24 -04:00
Andreas Hansson
5a1dea51d2 mem: Include WriteLineReq in cache demand stats
Somehow the WriteLineReq were never added to the list of commands
considered demand.
2016-04-21 04:48:20 -04:00
Andreas Hansson
a7c94f6e69 mem: Remove unused cache stats
Prune cache stats that are never actually used.
2016-04-21 04:48:19 -04:00
Andreas Hansson
13b9d4215d mem: Deallocate all write-queue entries when sent
This patch removes the write-queue entry tracking previously used for
uncacheable writes. The write-queue entry is now deallocated as soon
as the packet is sent. As a result we also forego the stats for
uncacheable writes. Additionally, there is no longer a need to attach
the write-queue entry to the packet.
2016-04-21 04:48:07 -04:00
Andreas Hansson
6c92ee49f1 mem: Align downstream cache packet creation in atomic and timing
This patch makes the control flow more uniform in atomic and timing,
ultimately making the code easier to understand.
2016-04-21 04:48:06 -04:00
Andreas Hansson
53d735b17e config: Add missing point of coherency to memcheck script
Bring in line with changes to the XBar class.
2016-04-21 04:48:04 -04:00
Andreas Sandberg
68a7752d73 scons: Fix Python 2.6 compatibility
Don't use Python 2.7-style with statements in the SConstruct file.
2016-04-18 10:40:50 +01:00
Andreas Sandberg
f819518158 style: Fix Python 2.6 compatibility
The style checker code needs to disable autojunk when diffing source
files using Python's difflib. Support for this was only introduced in
Python 2.7, which leads to a TypeError exception on older Python
version. This changeset adds a fallback mechanism for old Python
versions.
2016-04-18 10:31:38 +01:00
Joel Hestness
39e10ced03 ruby: Fix block_on behavior
Ruby's controller block_on behavior aimed to block MessageBuffer requests into
SLICC controllers when a Locked_RMW was in flight. Unfortunately, this
functionality only partially works: When non-Locked_RMW memory accesses are
issued to the sequencer to an address with an in-flight Locked_RMW, the
sequencer may pass those accesses through to the controller. At the controller,
a number of incorrect activities can occur depending on the protocol. In
MOESI_hammer, for example, an intermediate IFETCH will cause an L1D to L2
transfer, which cannot be serviced, because the block_on functionality blocks
the trigger queue, resulting in a deadlock. Further, if an intermediate store
arrives (e.g. from a separate SMT thread), the sequencer allows the request
through to the controller, and the atomicity of the Locked_RMW may be broken.

To avoid these problems, disallow the Sequencer from passing any memory
accesses to the controller besides Locked_RMW_Write when a Locked_RMW is in-
flight.
2016-04-15 12:34:02 -05:00
Bjoern A. Zeeb
edbf748181 arm,dev: remove PMU assertion hit on reset
Remve the assertion that we always need to add a delta larger than
zero as that does not seem to be true when we hit it in the
'PMU reset cycle counter to zero' case.

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-15 10:03:03 -05:00
Bjoern A. Zeeb
bc45e930e4 mem: FreeBSD does not provide MAP_NORESERVE either
Like OS X, FreeBSD does not support MAP_NORESERVE.
Handle accordingly and update comment.

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-15 10:02:58 -05:00
Abdul Mutaal Ahmad
1b46c175fc misc: Bugfix in TLM memInhibit Command
memInhibitAsserted() has been removed from packet.hh. This change has been
reflected in TLM based SystemC memory.
This patch also adds a number of panics asserting the SystemC memory only
sees requests it expects.

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-15 09:55:26 -05:00
Mohammad Alian
90cb9827be dist: config file for distributed switch
Distributed gem5 is the result of the convergence effort between
multi-gem5 and pd-gem5. It relies on the base multi-gem5 infrastructure
for packet forwarding, synchronisation and checkpointing but combines
those with the elaborated network switch model from pd-gem5.
2016-04-14 14:07:42 -04:00
Andreas Hansson
8127c4e7bf misc: Fix issues flagged by gcc 6
A few warnings (and thus errors) pop up after being added to -Wall:

1. -Wmisleading-indentation

In the auto-generated code there were instances of if/else blocks that
were not indented to gcc's liking. This is addressed by adding braces.

2. -Wshift-negative-value

gcc is clever enougn to consider ~0 a negative constant, and
rightfully complains. This is addressed by using mask() which
explicitly casts to unsigned before shifting.

That is all. Porting done.
2016-04-13 12:13:44 -04:00
Andreas Hansson
4b802a09c5 misc: Appease clang...again
Once again, clang is having issues with recently committed code.

Unfortunately HSAIL_X86 is still broken.
2016-04-12 05:28:39 -04:00
Andreas Hansson
d9193d1b20 stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
2016-04-09 12:13:40 -04:00
Curtis Dunham
1d61224a8b stats: update stats for thermals, indirect BP 2016-04-08 11:01:45 -05:00
Rekai Gonzalez Alberquilla
af27586fbc mem: Add priority to QueuedPrefetcher
Queued prefetcher entries now count with a priority field. The idea is to
add packets ordered by priority and then by age.

For the existing algorithms in which priority doesn't make sense, it is set
to 0 for all deferred packets in the queue.
2016-04-07 11:32:38 -05:00