Commit graph

1805 commits

Author SHA1 Message Date
Steve Reinhardt
9bf0961afc Rename builds more descriptively:
ALPHA -> ALPHA_SE (for Syscall Emulation)
KERNEL -> ALPHA_FS
KERN_TLASER -> ALPHA_FS_TL
Also renamed configs/kernel dir to configs/fullsys.

README:
build/SConstruct:
    Rename builds more descriptively.

--HG--
extra : convert_revision : f2bffb3ad0fc5068cc7fa20661ed9e4e7bc5b202
2005-06-02 16:15:43 -04:00
Nathan Binkert
ba73e1cc39 clean up command line stuff
sim/main.cc:
    Clean uo usage output and print usage when no options are given
    Don't accept mpy files anymore since we don't use them.

--HG--
extra : convert_revision : c3b16f602f301d2de12547285334c0037d829998
2005-06-02 11:20:31 -04:00
Nathan Binkert
0ee75f27b8 Fix-up some config issues
python/m5/config.py:
    Make NetworkBandwidth and MemoryBandwidth work
python/m5/objects/Ethernet.py:
    Make 1Gbps default for ethernet

--HG--
extra : convert_revision : 59e62f7e62624356ae8d7304598617f60667f040
2005-06-02 11:19:01 -04:00
Nathan Binkert
960672719a update copyrights that are spit out on the console.
--HG--
extra : convert_revision : e927fd48d2cc82d20478baeb05f58dce07a800e7
2005-06-02 11:17:45 -04:00
Steve Reinhardt
9238ceab25 More de-SimpleScalarization of cache code.
--HG--
extra : convert_revision : b310a0e8a02487302d4861cfa08543b6047a0ff7
2005-06-02 01:03:17 -04:00
Steve Reinhardt
e5b4bf28d9 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5

--HG--
extra : convert_revision : 71d4611b6d9496d3237c4d0cd46912a108ec8653
2005-06-02 00:08:09 -04:00
Erik Hallnor
f15d988a79 Change lru/iic parameter checks for licensing.
--HG--
extra : convert_revision : 5d5ae086d5e7981d49c68a2283ad2c08e27b4399
2005-06-01 23:14:10 -04:00
Steve Reinhardt
a69b418550 Get rid of unused sim/int_stats.* files.
--HG--
extra : convert_revision : 6b86e97fbadbd6f00c0bc52f0ab07fd7741f9818
2005-06-01 22:09:22 -04:00
Steve Reinhardt
62fa781fee Rename sim/universe.{cc,hh} to root.{cc,hh} (since the
object defined there was renamed Root long ago).

SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
base/misc.cc:
base/pollevent.cc:
base/pollevent.hh:
base/stats/events.cc:
base/trace.hh:
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/inst_queue_impl.hh:
cpu/pc_event.cc:
cpu/static_inst.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ide_disk.cc:
dev/pcidev.cc:
sim/builder.cc:
sim/eventq.cc:
sim/main.cc:
sim/root.cc:
sim/stat_control.cc:
    Rename sim/universe.{cc,hh} to root.{cc,hh}.

--HG--
rename : sim/universe.cc => sim/root.cc
extra : convert_revision : b8699e81e285253d66da75412e7bb2c251c0389a
2005-06-01 21:59:27 -04:00
Steve Reinhardt
8031cd93b5 Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
2005-06-01 21:44:00 -04:00
Steve Reinhardt
3304da9270 Get rid of obsolete simobj/SConscript
--HG--
extra : convert_revision : 2f2a5e1702a5ad09d80362e25a895e6181b2117c
2005-06-01 17:14:42 -04:00
Steve Reinhardt
3e7f660401 A few more config updates. Works with regression now.
configs/splash2/run.py:
    Update file for new config changes.
python/m5/config.py:
    - isParamContext() not defined any more
    - fix bug with re-assigning vectors over scalars
    and vice versa

--HG--
rename : configs/splash2/run.mpy => configs/splash2/run.py
extra : convert_revision : 2eb28a92f8de327f6dfddd01467c61e759275f6b
2005-06-01 17:08:45 -04:00
Steve Reinhardt
aad02f8088 Major cleanup of python config code.
Special mpy importer is gone; everything is just plain
Python now (funky, but straight-up).
May not completely work yet... generates identical ini
files for many configs/kernel settings, but I have yet
to run it against regressions.  This commit is for my
own convenience and won't be pushed until more testing
is done.

python/m5/__init__.py:
    Get rid of mpy_importer and param_types.
python/m5/config.py:
    Major cleanup.  We now have separate classes and
    instances for SimObjects.  Proxy handling and param
    conversion significantly reorganized.  No explicit
    instantiation step anymore; we can dump an ini file
    straight from the original tree.
    Still needs more/better/truer comments.
test/genini.py:
    Replace LoadMpyFile() with built-in execfile().
    Export __main__.m5_build_env.
python/m5/objects/AlphaConsole.py:
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/AlphaTLB.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/CoherenceProtocol.py:
python/m5/objects/Device.py:
python/m5/objects/DiskImage.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Ide.py:
python/m5/objects/IntrControl.py:
python/m5/objects/MemTest.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/Platform.py:
python/m5/objects/Process.py:
python/m5/objects/Repl.py:
python/m5/objects/Root.py:
python/m5/objects/SimConsole.py:
python/m5/objects/SimpleDisk.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
    Fixes for eliminating mpy_importer, and modified
    handling of frequency/latency params.
    Also renamed parent to Parent.

--HG--
rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py
rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py
rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py
rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py
rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py
rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py
rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py
rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py
extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76
2005-05-29 01:14:50 -04:00
Steve Reinhardt
ef5a7d91a5 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5

--HG--
extra : convert_revision : 475f25967577aa47d84b476c07ce0ddfe05078d0
2005-05-28 23:59:48 -04:00
Lisa Hsu
0b88d529dc ns_gige_reg.h, ns_gige.cc:
clean up code to eliminate license issues.

dev/ns_gige.cc:
dev/ns_gige_reg.h:
    clean up code to eliminate license issues.

--HG--
extra : convert_revision : 64adbd87faa5ce5ac6b9da4fd95b12796487c8f9
2005-05-28 21:54:32 -04:00
Kevin Lim
2a85931c5e Added copyright.
--HG--
extra : convert_revision : f6d53ac5130ea9f77f39f7c1aa35eeb1d5107599
2005-05-26 23:30:12 -04:00
Steve Reinhardt
8f0e0bd264 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5

--HG--
extra : convert_revision : 13696a8e526f7ded7555d009d03bdc7551557571
2005-05-25 16:06:12 -04:00
Steve Reinhardt
432e779fb0 Little debugging things.
cpu/base_cpu.cc:
    Get rid of leftover debugging code.

--HG--
extra : convert_revision : b33b2279499456b12a6242a9472ea5be724b37be
2005-05-24 16:37:30 -04:00
Steve Reinhardt
bfefc80310 Update mem trace reader params.
--HG--
extra : convert_revision : 03807971dacb23801895be45ea1582d2c345c021
2005-05-20 17:14:54 -04:00
Steve Reinhardt
9725c13a0b Minor changes to get new cpu to compile with FULL_SYSTEM.
cpu/beta_cpu/full_cpu.hh:
    Make cpu_id protected rather than private so derived
    classes can access it.
cpu/beta_cpu/regfile.hh:
    Get rid of troublesome debugging statement.

--HG--
extra : convert_revision : ae1f841697ea8d736579b8278eaf8fc6bdf3b6c5
2005-05-20 17:13:37 -04:00
Kevin Lim
c2fcac7c0d Fix up code for initial release. The main bug that remains is properly forwarding data from stores to loads, specifically when they are of differing sizes.
cpu/base_dyn_inst.cc:
    Remove unused commented out code.
cpu/base_dyn_inst.hh:
    Fix up comments.
cpu/beta_cpu/2bit_local_pred.cc:
    Reorder code to match header file.
cpu/beta_cpu/2bit_local_pred.hh:
    Update comments.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Remove useless comments.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
cpu/beta_cpu/alpha_full_cpu_impl.hh:
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/iew_impl.hh:
    Remove unused commented code.
cpu/beta_cpu/alpha_full_cpu.hh:
    Remove obsolete comment.
cpu/beta_cpu/alpha_impl.hh:
cpu/beta_cpu/full_cpu.hh:
    Alphabetize includes.
cpu/beta_cpu/bpred_unit.hh:
    Remove unused global history code.
cpu/beta_cpu/btb.hh:
cpu/beta_cpu/free_list.hh:
    Use full path in #defines.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/decode.hh:
    Reorder functions.
cpu/beta_cpu/commit_impl.hh:
    Remove obsolete commented code.
cpu/beta_cpu/fetch.hh:
    Remove obsolete comments.
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/rename_impl.hh:
    Remove commented code.
cpu/beta_cpu/full_cpu.cc:
    Remove useless defines.
cpu/beta_cpu/inst_queue.hh:
    Use full path for #defines.
cpu/beta_cpu/inst_queue_impl.hh:
    Reorder functions to match header file.
cpu/beta_cpu/mem_dep_unit.hh:
    Use full path name for #defines.
cpu/beta_cpu/ras.hh:
    Use full path names for #defines.  Remove mod operation.
cpu/beta_cpu/regfile.hh:
    Remove unused commented code, fix up current comments.
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Update programming style.

--HG--
extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a
2005-05-19 01:28:25 -04:00
Kevin Lim
e5721ce677 Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/current/m5
--HG--
extra : convert_revision : c403960153ed648e7da7251465ca9350ba10cd27
2005-05-17 14:34:46 -04:00
Steve Reinhardt
e8b62d05dd Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5

--HG--
extra : convert_revision : 5437b6fde4c09b8890d2bfa0cfba3d7e509a0f92
2005-05-15 07:43:12 -04:00
Steve Reinhardt
dd48c2c42c Fix "no supplier" bug.
--HG--
extra : convert_revision : 01549db31d2094c58c6875fbbf79d4e07e7e39f9
2005-05-15 00:34:27 -04:00
Steve Reinhardt
9dec81719e More cleanup of fetch code.
--HG--
extra : convert_revision : a2279283be76341467e228ad1d56989a2be383eb
2005-05-14 19:42:46 -04:00
Steve Reinhardt
16dcebf4c4 Add mem_trace parameter to BaseCache.
python/m5/objects/BaseCache.mpy:
    Add mem_trace parameter.

--HG--
extra : convert_revision : a0bab53fabd7426eee5ca9c845c02a6ac2e1722f
2005-05-13 15:01:42 -04:00
Steve Reinhardt
581ef3c076 panic vs fatal fixes in bus.cc
base/misc.hh:
    Add some comments explaining the difference between
    panic() and fatal().

--HG--
extra : convert_revision : 876f0c98276fa1060c0589dc179022a297a8ed2e
2005-05-13 00:28:42 -04:00
Steve Reinhardt
ea18fda771 Force pipeline drain on first instruction of async interrupt handler.
Done by marking DynInst as serializing... requires adding the ability
to check both DynInst and StaticInst for serializing behavior.

--HG--
extra : convert_revision : 00db3e16d3b13dd9663f5a9f1bd8f724ed499914
2005-05-12 19:25:38 -04:00
Steve Reinhardt
31db1f3c09 Get rid of unused SMT code from FullCPU.
--HG--
extra : convert_revision : 7a047b36718a44a8f3a43e3c0f54ca796d19f10a
2005-05-12 15:36:42 -04:00
Steve Reinhardt
480dd22d02 Add definitions for memory trace writers.
--HG--
extra : convert_revision : bb27c2a2ba8f97f186b712165db9a25f3fe61dda
2005-05-09 12:12:07 -04:00
Kevin Lim
c03e97b62d Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/current/m5
--HG--
extra : convert_revision : b868e7920eaa3682c6123651f0c598673ebb7f22
2005-05-04 14:41:36 -04:00
Ron Dreslinski
3b0464127e Add support for dedicated 1GHz Simple CPU
New examples of test.py files in ~rdreslin/jobs/ancs0 and ~rdreslin/cpt/ancs0

--HG--
extra : convert_revision : c2337874199fae9cbd43da9dbc3b9bd85ea2c92e
2005-05-03 14:42:58 -04:00
Kevin Lim
61d95de4c8 Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
    Remove OOO CPU stuff.
arch/alpha/faults.hh:
    Add fake memory fault.  This will be removed eventually.
arch/alpha/isa_desc:
    Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
    Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
    Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
    Remove asid.
cpu/beta_cpu/comm.hh:
    Remove global history field.
cpu/beta_cpu/commit.hh:
    Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
    Update some of the full system code so it compiles.  Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
    Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
    Add debug function.
cpu/beta_cpu/decode_impl.hh:
    Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
    Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
    Changed some of the full system code so it compiles.  Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
    Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
    Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
    Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
    New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
    Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
    Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
    Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
    Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
    Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
    Remove OOO CPU stuff.  Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
    Extra forward declares added due to compile error.

--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-03 10:56:47 -04:00
Nathan Binkert
90422716f8 Fix ethernet configuration
--HG--
extra : convert_revision : 9ee6e620b722d39d234b15785852a6cc00ffe041
2005-05-02 19:05:20 -04:00
Nathan Binkert
6606a37546 Skip calibrate delay again.
kern/linux/linux_system.cc:
    calibrate delay starts three instructions after the symbol now.

--HG--
extra : convert_revision : f9c2bed3bca1f3394801fe7696cfff870443c204
2005-05-02 19:01:11 -04:00
Nathan Binkert
364f6e3235 Make sinic work with mpy
dev/sinic.cc:
dev/sinic.hh:
    Fix sinic parameters. (header_bus -> io_bus)
python/m5/objects/Ethernet.mpy:
    Add simobj definitions for sinic.

--HG--
extra : convert_revision : 77d5b80bd1f1708329b263fb48965d7f555cc9d1
2005-05-02 19:00:11 -04:00
Nathan Binkert
5921d6beb8 workaround configuration bug in tick is ps.
--HG--
extra : convert_revision : 301b6e4d590efc7a4d11959a932d5349edc59041
2005-05-02 18:56:50 -04:00
Nathan Binkert
1760925f73 Improve checkpointing of ethernet packets a bit.
dev/etherpkt.cc:
    Don't try to suck in the packet if the length is zero.

--HG--
extra : convert_revision : 7212f3b677777fbce301f0613b9f513bb9fe057e
2005-05-02 18:55:39 -04:00
Nathan Binkert
306a4f2014 Better configurations for checkpointing. Add more NIC options.
--HG--
extra : convert_revision : d0b9ccbcb4ac14f0d305bfcbfb9a041dfb5d3465
2005-05-02 18:54:36 -04:00
Ron Dreslinski
a35c6fd4c6 Make sure to just do the dma No Allocation on reads
--HG--
extra : convert_revision : f5d0b6753958c36fd3678c61b5e9af943e24d517
2005-05-02 18:02:51 -04:00
Ron Dreslinski
13d0e7c626 Add environment parameter for Allocation policy of DMA's
--HG--
extra : convert_revision : 444952065b0508c083e8c64fa5f9f5a761787900
2005-05-02 14:25:54 -04:00
Kevin Lim
6191d3e444 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : ac0788599c365b2d7fe0870f0fea4b62c3b3ef22
2005-05-02 14:16:33 -04:00
Ron Dreslinski
950ce813c4 Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/clean

--HG--
extra : convert_revision : eb92d2799c76fad09f6b5a9476e4e9fc7c8dbfca
2005-04-30 12:54:28 -04:00
Ron Dreslinski
cf88d0e271 Handle no_allocates as needing the response in miss_queue, like uncacheables
Add support for hit under miss of a no allocate (It seems as though DMA reads to the same block happen close together, is this an artifact of the header/payload splitting)
Make sure to respond to all targets of a no_allocate request

--HG--
extra : convert_revision : a9d733f499face4039929524573ffc9500e93d83
2005-04-30 12:53:58 -04:00
Nathan Binkert
849c954adf Cleanup rcS files. Make sure there are enough tracked connections.
Delay before singalling peer to make sure that the peer is ready

configs/boot/nat-netperf-server.rcS:
    delay before singalling to make sure that the natbox is ready
configs/boot/nat-netperf-stream-client.rcS:
    increase the number of tracked connections
configs/boot/nat-spec-surge-client.rcS:
configs/boot/nfs-client-nhfsstone.rcS:
configs/boot/nfs-client-smallb.rcS:
configs/boot/nfs-client-tcp-smallb.rcS:
configs/boot/nfs-client-tcp.rcS:
configs/boot/nfs-client.rcS:
configs/boot/nfs-server.rcS:
configs/boot/spec-surge-client.rcS:
configs/boot/spec-surge-server.rcS:
configs/boot/surge-client.rcS:
configs/boot/surge-server.rcS:
    increase the number of tracked connections
    cleanup
configs/boot/nat-spec-surge-server.rcS:
configs/boot/natbox-netperf.rcS:
configs/boot/nfs-server-nhfsstone.rcS:
    delay before singalling to make sure that the natbox is ready
    increase the number of tracked connections
    cleanup
configs/boot/natbox-spec-surge.rcS:
    delay before singalling to make sure that the natbox is ready
    increase the number of tracked connections

--HG--
extra : convert_revision : 9faa5ec11c9c02fed3d1cff922ca42c41d364204
2005-04-30 11:00:43 -04:00
Ron Dreslinski
602a489573 Add suport for no allocation of cache block on a dma read passing through a cache from the cpu-side interface
--HG--
extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a
2005-04-29 21:01:43 -04:00
Ron Dreslinski
e07fee31cb Clean up output for pc break events, and remove a unneeded break event.
cpu/pc_event.cc:
    Add a newline to the printout to clean up output
kern/linux/linux_system.cc:
    Remove the die_if_kernel pc break event, it is being called when not the kernel and leads to unneeded printouts

--HG--
extra : convert_revision : c359532db31c961074894cc6c44c8452592caca8
2005-04-28 17:24:04 -04:00
Ron Dreslinski
2bb9126a7a Make ip_conntrack table size larger
--HG--
extra : convert_revision : bda54b29cb15144907b186f06517477dea13ba06
2005-04-28 16:13:30 -04:00
Nathan Binkert
3154e2a0c7 Add the m5 parameter to the ns83820 device model so that we
can pass simulator specific options to the device driver.

dev/ns_gige.cc:
    Add the m5 register and parameter to the ns83820 device model
    so that we can pass simulator specific options to the device
    driver.
dev/ns_gige.hh:
dev/ns_gige_reg.h:
    Add the m5 register to the ns83820 device model

--HG--
extra : convert_revision : 84674887560fa3b607e725b8e5bc8272761fcf09
2005-04-24 21:32:32 -04:00
Nathan Binkert
6f9dba3cec cleanup mpy file
--HG--
extra : convert_revision : ddde8f1b60dfa0c637d82d9217e713f071af6ccb
2005-04-24 21:28:54 -04:00