Commit graph

4438 commits

Author SHA1 Message Date
Gabe Black
869a046e41 O3: Fix a style bug in O3. 2011-02-02 23:34:14 -08:00
Gabe Black
cb22bead7d X86: Get rid of the stupd microop. 2011-02-02 19:57:12 -08:00
Gabe Black
eabbdbee63 X86: Replace the stupd microop with a store/update sequence. 2011-02-02 19:56:38 -08:00
Gabe Black
75d34c14fc Time: Add serialization functions to the Time class. 2011-02-02 18:05:03 -08:00
Gabe Black
119f5f8e94 X86: Add L1 caches for the TLB walkers.
Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.
2011-02-01 18:28:41 -08:00
Gabe Black
4b4cd0303e Fault: Move the definition of NoFault from faults.hh to fault.hh.
Moving the definition of NoFault into fault.hh doesn't bring any new
dependencies with it, and allows some files to include just fault.hh which has
less baggage. NoFault will still be available to everything that includes
faults.hh because it includes fault.hh.
2011-01-31 13:13:00 -08:00
Nathan Binkert
048b1e5843 refcnt: Change things around so that we handle constness correctly.
To use a non const pointer:
typedef RefCountingPtr<Foo> FooPtr;

To use a const pointer:
typedef RefCountingPtr<const Foo> ConstFooPtr;
2011-01-22 21:48:06 -08:00
Steve Reinhardt
5c99ae60b8 checkpointing: fix bug from curTick accessor conversion.
Regex replacement of curTick with curTick() accidentally
changed checkpoint key string for serialization but not
for unserialization.
2011-01-20 22:13:33 -08:00
Gabe Black
ddeaf1252f TimeSync: Use the new setTick and getTick functions. 2011-01-19 16:22:23 -08:00
Gabe Black
23bab6783b Time: Add setTick and getTick functions to the Time class. 2011-01-19 16:22:15 -08:00
Gabe Black
a368fba7d4 Time: Add a mechanism to prevent M5 from running faster than real time.
M5 skips over any simulated time where it doesn't have any work to do. When
the simulation is active, the time skipped is short and the work done at any
point in time is relatively substantial. If the time between events is long
and/or the work to do at each event is small, it's possible for simulated time
to pass faster than real time. When running a benchmark that can be good
because it means the simulation will finish sooner in real time. When
interacting with the real world through, for instance, a serial terminal or
bridge to a real network, this can be a problem. Human or network response time
could be greatly exagerated from the perspective of the simulation and make
simulated events happen "too soon" from an external perspective.

This change adds the capability to force the simulation to run no faster than
real time. It does so by scheduling a periodic event that checks to see if
its simulated period is shorter than its real period. If it is, it stalls the
simulation until they're equal. This is called time syncing.

A future change could add pseudo instructions which turn time syncing on and
off from within the simulation. That would allow time syncing to be used for
the interactive parts of a session but then turned off when running a
benchmark using the m5 utility program inside a script. Time syncing would
probably not happen anyway while running a benchmark because there would be
plenty of work for M5 to do, but the event overhead could be avoided.
2011-01-19 11:48:00 -08:00
Matt Horsnell
77853b9f52 O3: Fix itstate prediction and recovery.
Any change of control flow now resets the itstate to 0 mask and 0 condition,
except where the control flow alteration write into the cpsr register. These
case, for example return from an iterrupt, require the predecoder to recover
the itstate.

As there is a window of opportunity between the return from an interrupt
changing the control flow at the head of the pipe and the commit of the update
to the CPSR, the predecoder needs to be able to grab the ITstate early. This
is now handled by setting the forcedItState inside a PCstate for the control
flow altering instruction.

That instruction will have the correct mask/cond, but will not have a valid
itstate until advancePC is called (note this happens to advance the execution).
When the new PCstate is copy constructed it gets the itstate cond/mask, and
upon advancing the PC the itstate becomes valid.

Subsequent advancing invalidates the state and zeroes the cond/mask. This is
handled in isolation for the ARM ISA and should have no impact on other ISAs.

Refer arch/arm/types.hh and arch/arm/predecoder.cc for the details.
2011-01-18 16:30:05 -06:00
Matt Horsnell
b13a79ee71 O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA. 2011-01-18 16:30:05 -06:00
Matt Horsnell
c98df6f8c2 O3: Don't test misprediction on load instructions until executed. 2011-01-18 16:30:05 -06:00
Ali Saidi
1167ef19cf O3: Keep around the last committed instruction and use for squashing.
Without this change 0 is always used for the youngest sequence number if
a squash occured and the ROB was empty (E.g. an instruction is marked
serializeAfter or a fetch stall prevents other instructions from issuing).
Using 0 there is a race to rename where an instruction that committed the
same cycle as the squashing instruction can have it's renamed state undone
by the squash using sequence number 0.
2011-01-18 16:30:05 -06:00
Ali Saidi
ea058b14da O3: Don't try to scoreboard misc registers.
I'm not positive this is the correct fix, but it's working right now.
Either we need to do something like this, prevent the misc reg from being renamed at all,
or there something else going on. We need to find the root cause as to why
this is only a problem sometimes.
2011-01-18 16:30:05 -06:00
Matt Horsnell
adbd84ab9f ARM: The ARM decoder should not panic when decoding undefined holes is arch.
This can abort simulations when the fetch unit runs ahead and speculatively
decodes instructions that are off the execution path.
2011-01-18 16:30:05 -06:00
Matt Horsnell
11bef2ab38 O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf. 2011-01-18 16:30:05 -06:00
Matt Horsnell
62f2097917 O3: Fix mispredicts from non control instructions.
The squash inside the fetch unit should not attempt to remove them from the
branch predictor as non-control instructions are not pushed into the predictor.
2011-01-18 16:30:05 -06:00
Matt Horsnell
5ebf3b2808 O3: Fixes the way prefetches are handled inside the iew unit.
This patch prevents the prefetch being added to the instCommit queue twice.
2011-01-18 16:30:02 -06:00
Ali Saidi
ee9a331fe5 O3: Support timing translations for O3 CPU fetch. 2011-01-18 16:30:02 -06:00
Ali Saidi
0f9a3671b6 ARM: Add support for moving predicated false dest operands from sources. 2011-01-18 16:30:02 -06:00
Min Kyu Jeong
96375409ea O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.
When this condition occurs the cpu should restart the fetch stage to fetch from
the original execution path. Fault handling in the commit stage is cleaned up a
little bit so the control flow is simplier. Finally, if an instruction is being
used to carry a fault it isn't executed, so the fault propagates appropriately.
2011-01-18 16:30:01 -06:00
Ali Saidi
965a01d913 ARM: Use an actual NOP instead of a instruction that happens to do nothing 2011-01-18 16:30:01 -06:00
Ali Saidi
a3232b534b ARM: fix mismatched new/delete. 2011-01-18 16:30:01 -06:00
Gabe Black
a39096a8c3 Unit tests: Convert the refcnttest unit test to use the new EXPECT macros. 2011-01-18 01:27:04 -08:00
Gabe Black
c04571d601 Unit tests: Define a header file for common unit testing functions/macros. 2011-01-18 01:26:55 -08:00
Nathan Binkert
318bfe9d4f time: improve time datastructure
Use posix clock functions (and librt) if it is available.
Inline a bunch of functions and implement more operators.
* * *
time: more cleanup
2011-01-15 07:48:25 -08:00
Nilay Vaish
c82a8979a3 Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.

I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.

Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.

Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.

All the protocols have been modified to conform with the new interface.
2011-01-17 18:46:16 -06:00
Gabe Black
371603f12c SPARC: Adjust the "call" instruction so R15 doesn't get marked as a source. 2011-01-15 15:30:17 -08:00
Nilay Vaish
47ba26f6b3 Ruby: Fixes MESI CMP directory protocol
The current implementation of MESI CMP directory protocol is broken.
This patch, from Arkaprava Basu, fixes the protocol.
2011-01-13 22:17:11 -06:00
Korey Sewell
cd5a7f7221 inorder: fix RUBY_FS build
the current code was using incorrect dummy instruction in interrupts function
2011-01-12 11:52:29 -05:00
Nathan Binkert
bd18ac8287 ruby: get rid of ruby's Debug.hh
Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace
2011-01-10 11:11:20 -08:00
Nathan Binkert
8e262adf4f stats: Add a histogram statistic type 2011-01-10 11:11:17 -08:00
Nathan Binkert
b9ddc1a726 stats: fix stat test from curTick change 2011-01-10 11:11:17 -08:00
Nathan Binkert
ff592e0ed1 stats: fix the distribution stat 2011-01-10 11:11:16 -08:00
Gabe Black
ae7e67f334 Root: Get rid of unnecessary includes in root.cc. 2011-01-10 04:53:34 -08:00
Gabe Black
df14312e08 Curtick: Fix mysql.cc build needing curTick. 2011-01-10 04:53:20 -08:00
Gabe Black
dc64732dee RefCount: Add a unit test for reference counting pointers.
This test exercises each of the functions in the reference counting pointer
implementation individually (except get()) and verifies they have some
minimially expected behavior. It also checks that reference counted objects
are freed when their usage count goes to 0 in some basic situations,
specifically a pointer being set to NULL and a pointer being deleted.
2011-01-10 03:56:42 -08:00
Steve Reinhardt
6f1187943c Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
2011-01-07 21:50:29 -08:00
Steve Reinhardt
c22be9f2f0 stats: rename StatEvent() function to schedStatEvent().
This follows the style rules and is more descriptive.
2011-01-07 21:50:29 -08:00
Steve Reinhardt
94807214c4 sim: clean up CountedDrainEvent slightly.
There's no reason for it to derive from SimLoopExitEvent.
This whole drain thing needs to be redone eventually,
but this is a stopgap to make later changes to
SimLoopExitEvent feasible.
2011-01-07 21:50:29 -08:00
Steve Reinhardt
030736a69b sim: delete unused CheckSwapEvent code.
There's no way to even create one of these anymore.
2011-01-07 21:50:29 -08:00
Steve Reinhardt
df9f99567d pseudoinst: get rid of mainEventQueue references.
Avoid direct references to mainEventQueue in pseudo-insts
by indirecting through associated CPU object.
Made exitSimLoop() more flexible to enable some of these.
2011-01-07 21:50:29 -08:00
Steve Reinhardt
d60c293bbc inorder: replace schedEvent() code with reschedule().
There were several copies of similar functions that looked
like they all replicated reschedule(), so I replaced them
with direct calls.  Keeping this separate from the previous
cset since there may be some subtle functional differences
if the code ever reschedules an event that is scheduled but
not squashed (though none were detected in the regressions).
2011-01-07 21:50:29 -08:00
Steve Reinhardt
214cc0fafc inorder: get rid of references to mainEventQueue.
Events need to be scheduled on the queue assigned
to the SimObject, not on the global queue (which
should be going away).
Also cleaned up a number of redundant expressions
that made the code unnecessarily verbose.
2011-01-07 21:50:29 -08:00
Steve Reinhardt
d650f4138e scons: show sources and targets when building, and colorize output.
I like the brevity of Ali's recent change, but the ambiguity of
sometimes showing the source and sometimes the target is a little
confusing.  This patch makes scons typically list all sources and
all targets for each action, with the common path prefix factored
out for brevity.  It's a little more verbose now but also more
informative.

Somehow Ali talked me into adding colors too, which is a whole
'nother story.
2011-01-07 21:50:13 -08:00
Nilay Vaish
d36cc62c11 Ruby: Updates MOESI Hammer protocol
This patch changes the manner in which data is copied from L1 to L2 cache in
the implementation of the Hammer's cache coherence protocol. Earlier, data was
copied directly from one cache entry to another. This has been broken in to
two parts. First, the data is copied from the source cache entry to a
transaction buffer entry. Then, data is copied from the transaction buffer
entry to the destination cache entry.

This has been done to maintain the invariant - at any given instant, multiple
caches under a controller are exclusive with respect to each other.
2011-01-04 21:40:49 -06:00
Gabe Black
498ea0bdab Params: Print the IP components in the right order. 2011-01-04 17:11:49 -05:00
Steve Reinhardt
89cf3f6e85 Move sched_list.hh and timebuf.hh from src/base to src/cpu.
These files really aren't general enough to belong in src/base.
This patch doesn't reorder include lines, leaving them unsorted
in many cases, but Nate's magic script will fix that up shortly.

--HG--
rename : src/base/sched_list.hh => src/cpu/sched_list.hh
rename : src/base/timebuf.hh => src/cpu/timebuf.hh
2011-01-03 14:35:47 -08:00