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O3: Fixes the way prefetches are handled inside the iew unit.

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This patch prevents the prefetch being added to the instCommit queue twice.
This commit is contained in:
Matt Horsnell 2011-01-18 16:30:02 -06:00
parent ee9a331fe5
commit 5ebf3b2808
3 changed files with 13 additions and 4 deletions
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3
src/arch/arm/faults.hh
View file

@ -92,7 +92,8 @@ class ArmFault : public FaultBase
// to allow the translation function to inform
// the memory access function not to proceed
// for a Prefetch that misses in the TLB.
PrefetchTLBMiss
PrefetchTLBMiss = 0x1f,
PrefetchUncacheable = 0x20
};
struct FaultVals

8
src/arch/arm/tlb.cc
View file

@ -556,9 +556,15 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
outerAttrs: %d\n",
te->shareable, te->innerAttrs, te->outerAttrs);
setAttr(te->attributes);
if (te->nonCacheable)
if (te->nonCacheable) {
req->setFlags(Request::UNCACHEABLE);
// Prevent prefetching from I/O devices.
if (req->isPrefetch()) {
return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
}
}
switch ( (dacr >> (te->domain * 2)) & 0x3) {
case 0:
domainFaults++;

6
src/cpu/o3/iew_impl.hh
View file

@ -1222,8 +1222,7 @@ DefaultIEW<Impl>::executeInsts()
// Execute instruction.
// Note that if the instruction faults, it will be handled
// at the commit stage.
if (inst->isMemRef() &&
(!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
if (inst->isMemRef()) {
DPRINTF(IEW, "Execute: Calculating address for memory "
"reference.\n");
@ -1232,6 +1231,9 @@ DefaultIEW<Impl>::executeInsts()
// Loads will mark themselves as executed, and their writeback
// event adds the instruction to the queue to commit
fault = ldstQueue.executeLoad(inst);
if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
fault = NoFault;
}
} else if (inst->isStore()) {
fault = ldstQueue.executeStore(inst);