arch/isa_parser.py:
Expanded the capability of the InstObjParams constructor to allow adding in extra keys for use in templates. These are added as key, value tuples as optional arguements.
arch/sparc/isa/base.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/priv.isa:
The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor.
arch/sparc/isa/decoder.isa:
Fixed up alot of instructions, and fixed indentation.
arch/sparc/isa/formats/integerop.isa:
The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. Also changed the immediate values to be signed.
base/traceflags.py:
Added SPARC traceflag
configs/test/hello_sparc:
Recompiled without -mflat
cpu/cpu_exec_context.cc:
Used the regfile clear function rather than memsetting to 0.
--HG--
extra : convert_revision : b9da6f264f3ebc4ce1815008dfff7f476b247ee9
arch/mips/isa/formats/branch.isa:
let user know that we alter r31 in disassembly
arch/mips/isa_traits.cc:
add copyRegs function ...
comment out serialize float code for now
arch/mips/isa_traits.hh:
make FloatRegFile a class ... change values of architectural regs
arch/mips/process.cc:
change MIPS to Mips
base/loader/elf_object.cc:
get global pointer initialized to a value
base/loader/elf_object.hh:
Add global_ptr to elf_object constructor
base/loader/object_file.hh:
MIPS to Mips
base/traceflags.py:
SimpleCPU trace flag
cpu/simple/cpu.cc:
DPRINTF flags for SimpleCPU
cpu/static_inst.hh:
Add Decoder functions to static_inst.hh
--HG--
extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
SConscript:
Get rid of the pc_sample stuff and move to the new profiling stuff
base/traceflags.py:
DPRINTF Stack stuff
cpu/base.cc:
cpu/base.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
Add profiling stuff
kern/kernel_stats.hh:
Use a smart pointer
sim/system.cc:
sim/system.hh:
Create a new symbol table that has all of the symbols for a
particular system
util/stats/categories.py:
change around the categories, add categories for function
profiling stuff
util/stats/profile.py:
No profile parsing and display code to deal with function
profiling stuff, graph, dot, and text outputs.
--HG--
extra : convert_revision : b3de0cdc8bd468e42647966e2640ae009bda9eb8
SConscript:
Add prefetcher to the compilation
base/traceflags.py:
Add a trace flag for hardware prefetches
--HG--
extra : convert_revision : bc210192a2b75b1470b2cd9d5d470fc61cb11315
SConscript:
Include new files.
arch/alpha/isa_desc:
Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Fixes for gcc-3.4.
Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
Use new params pointer in BaseCPU.
Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
Remove unused global variable.
cpu/static_inst.hh:
Include OoODynInst for new lightweight OoO CPU
--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
a faulting instruction is the fault handler, which appears as an independent
instruction to the timing model. New code will stall fetch and not fetch the
fault handler as long as there's a faulting instruction in the pipeline (i.e.,
the faulting inst has to commit first).
Also fix Ali's bad-address assertion that doesn't apply to full system.
Added some more debugging support in the process. Hopefully we'll move to the new
cpu model soon and we won't need it anymore.
arch/alpha/alpha_memory.cc:
Reorganize lookup() so we can trace the result of the lookup as well.
arch/alpha/isa_traits.hh:
Add NoopMachInst (so we can insert them in the pipeline on ifetch faults).
base/traceflags.py:
Replace "Dispatch" flag with "Pipeline" (since I added similar
DPRINTFs in other pipe stages).
cpu/exetrace.cc:
Change default for printing mis-speculated instructions to true (since
that's often what we want, and right now you can't change it from the
command line...).
--HG--
extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc
base/traceflags.py:
Merge extra new CPU flags
cpu/static_inst.hh:
Include all the execute functions in static_inst_impl.hh
--HG--
extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
base/traceflags.py:
Add new commit rate trace flag.
build/SConstruct:
Add extra option for efence.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Use function calls instead of direct indexing (avoids confusion).
cpu/beta_cpu/commit_impl.hh:
Add commit rate trace output (might not be worthwhile in the future).
cpu/beta_cpu/decode_impl.hh:
Remove some older hacks. Fix it so that the isntruction properly sets its next
PC to the one calculated by the branch.
cpu/beta_cpu/fetch_impl.hh:
Remove old commented code.
cpu/beta_cpu/iew_impl.hh:
Add extra check to ensure that the instruction is valid.
cpu/beta_cpu/regfile.hh:
Include trace file.
--HG--
extra : convert_revision : 4ee1dc88f8a5ed9b65486c6c111a3718a8040e42
Also change to ref counted DynInst.
SConscript:
Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
Specify the template parameter for AlphaDynInst
base/traceflags.py:
Add load store queue, store set, and mem dependence unit to the
list of trace flags.
cpu/base_dyn_inst.cc:
Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
Change DynInst to be RefCounted, add flag to clear whether or not this
instruction can commit. This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
AlphaDynInst has been changed to be templated, so now this CC file
is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
Changed AlphaDynInst to be templated on Impl. Removed some unnecessary
functions.
cpu/beta_cpu/alpha_full_cpu.cc:
AlphaFullCPU has been changed to be templated, so this CC file is now
just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
Update it to reflect AlphaDynInst and AlphaFullCPU being templated
on Impl. Also removed time buffers from here, as they are really
a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
need to specifically declare any parameters that are already in the
BaseFullCPU.
cpu/beta_cpu/comm.hh:
Changed the structure of the time buffer communication structs. Now
they include the size of the packet of instructions it is sending.
Added some parameters to the backwards communication struct, mainly
for squashing.
cpu/beta_cpu/commit.hh:
Update typenames to reflect change in location of time buffer structs.
Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
Formatting changes mainly. Also sends back proper information
on branch mispredicts so that the bpred unit can update itself.
Updated behavior for non-speculative instructions (stores, any
other non-spec instructions): once they reach the head of the ROB,
the ROB signals back to the IQ that it can go ahead and issue the
non-speculative instruction. The instruction itself is updated so that
commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
Added branch prediction unit, mem dependence prediction unit, load
store queue. Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
Changed typedefs to reflect change in location of time buffer structs
and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
Continues to buffer instructions even while unblocking now. Changed
how it loops through groups of instructions so it can properly block
during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
Changed typedefs to reflect change in location of time buffer structs
and the change to ref counted DynInsts. Also added in branch
brediction unit.
cpu/beta_cpu/fetch_impl.hh:
Add in branch prediction. Changed how fetch checks inputs and its
current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
Changed int regs and float regs to logically use one flat namespace.
Future change will be moving them to a single scoreboard to conserve
space.
cpu/beta_cpu/free_list.hh:
Mostly debugging statements. Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
Added in some debugging statements. Updated BaseFullCPU to take
a params object.
cpu/beta_cpu/full_cpu.hh:
Added params class within BaseCPU that other param classes will be
able to inherit from. Updated typedefs to reflect change in location
of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
Updated typedefs to reflect change in location of time buffer structs
and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
Added in load store queue, updated iew to be able to execute non-
speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
Updated change to ref counted DynInsts. Changed inst queue to hold
non-speculative instructions as well, which are issued only when
commit signals backwards that a nonspeculative instruction is at
the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
Updated to allow for non-speculative instructions to be in the inst
queue. Also added some debug functions.
cpu/beta_cpu/regfile.hh:
Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
Changed int and float reg behavior to use a single flat namespace. In
the future, the rename maps can be combined to a single rename map to
save space.
cpu/beta_cpu/rename_map.hh:
Added destructor.
cpu/beta_cpu/rob.hh:
Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
Updated forward declaration for AlphaDynInst now that it is templated.
--HG--
extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
structures.
Added event to print out currently running task
base/traceflags.py:
Added Thread trace flag
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
Added event to print out currently running task
--HG--
extra : convert_revision : 94347dbaf90f39eb40467b2a43b4628a3deafc6c
base/mysql.hh:
Trace sql queries
base/traceflags.py:
Add a trace flag to trace sql queries
--HG--
extra : convert_revision : dc25abb474db7334529b791a7aa90f8178ea59ea
SConscript:
add these files for partitioned caches
base/traceflags.py:
add Split as a traceflag
--HG--
extra : convert_revision : 6aa8f7c389ee1145b33be006c820236f11f5397c
'cd build; scons' will build ALPHA/m5.debug.
Use e.g. 'scons KERNEL/m5.opt' to build other binaries.
Read the comments in build/SConstruct for more details.
base/traceflags.py:
Take basename of generated cc/hh files from command line instead
of hardwiring them. Lets us call the script from a different
directory and still have the files end up in the right place
(e.g. "base/traceflags.py base/traceflags").
--HG--
extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
base/traceflags.py:
removed TsunamiUart/TlaserUart and added a plain Uart
dev/alpha_console.cc:
updated for new simconsole
dev/platform.hh:
added a uart member to platform
dev/simconsole.cc:
dev/simconsole.hh:
removed lots of legacy code, it should all be ours now.
converted tabs to 8 spaces
added our copyright
dev/tsunami.cc:
uses simconsole.hh rather than console.hh
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
never needed console.hh
dev/tsunami_io.hh:
this does need eventq.hh and it just happend to be working whenn console.hh was
included everywhere
dev/tsunamireg.h:
added a couple more 8250/16550 uart defines
dev/uart.cc:
new uart code, rewritten to support both tlaser and tsunami (both a 8250 and 8530
uart).
dev/uart.hh:
updated for new uart, legacy code removed
--HG--
rename : dev/console.cc => dev/simconsole.cc
rename : dev/console.hh => dev/simconsole.hh
rename : dev/tsunami_uart.cc => dev/uart.cc
rename : dev/tsunami_uart.hh => dev/uart.hh
extra : convert_revision : e663352d49d4c2d3c95643030cf73c0e85ba2f08
base/traceflags.py:
added some more traceflags for ethernet to break it up better
dev/etherpkt.hh:
since we are not network host order, must reverse bytes for these typechecks.
also, overload isTcp/UdpPkt to take an argument so you don't have to reget the ip header if you've already got one.
dev/ns_gige.cc:
1) add some functions that reverse Endianness so we can generate adn evaluate checksum adn dprintf data accurately/more understandably
2) forget about the implementation of fifo fill/drain thresholds, it's not used by the driver much, nor does it matter with use sending/receiving in whole packets anyway.
get rid of teh associated variables.
3) get rid of txFifoCnt the variable, it's redundant and unnecessary, just use txFifoAvail.
4) change io_enable to ioEnable, just to be picky.
5) modify some DPRINTF's to be clearer, also added a lot, and spread them into better traceflag categories
6) fix the device bug! it's the intrTick = 0 at teh beginning of cpuInterrupt().
7) clear some bools in regsReset() so they don't holdover wrong state
8) fix pseudo header generation for Tcp checksumming to account for network order
dev/ns_gige.hh:
change io_enable to ioEnable, get rid of fill/drain thresh related variables and txFifoCnt, which is redundant
--HG--
extra : convert_revision : c538b75731f3c9e04354f57e6df9a40aeca5096d
Mostly a matter of keeping prefetches to invalid addrs
from messing up VM IPRs. Also discovered that wh64s were
not being treated as prefetches, when they really should be
(for the most part, anyway).
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
- Add NO_FAULT MemReq flag to indicate references that should not
cause page faults (i.e., prefetches).
arch/alpha/ev5.cc:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
- Add Fault trace flag.
arch/alpha/isa_desc:
- Add NO_FAULT MemReq flag to indicate references that should not
cause page faults (i.e., prefetches).
- Mark wh64 as a "data prefetch" instruction so it gets controlled
properly by the FullCPU data prefetch control switch.
- Align wh64 EA in decoder so issue stage doesn't need to worry about it.
arch/alpha/isa_traits.hh:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
base/traceflags.py:
- Add Fault trace flag.
cpu/simple_cpu/simple_cpu.hh:
- Pass MemReq flags to writeHint() operation.
cpu/static_inst.hh:
Update comment re: prefetches.
--HG--
extra : convert_revision : 62e466b0f4c0ff9961796270fa2e371ec24bcbb6
base/stats/mysql.hh:
Rename of Statsistics namespace to stats... merge from head
--HG--
extra : convert_revision : a5a7f6268b35e75fba1b1800a74fcd6dbd09d974
of events into the database for a given run.
base/stats/mysql.cc:
base/stats/mysql.hh:
reorganize mysql stat stuff so that other stuff can use
the same database connection
base/traceflags.py:
Trace flag to print out events
--HG--
extra : convert_revision : 4d502532ed0ba40b42baefee46b2c99defcc620c
arch/alpha/alpha_memory.cc:
change to the main m5 tree convention for naming
base/traceflags.py:
add ide and pciconfigall traceflags
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kill some old binning styled stuff
--HG--
extra : convert_revision : 0558878906817975a714b1c7c08f9ee405468535
instead of with the source code. This will hopefully be especially
useful when we're generating dozens of files when we flesh out the
object description stuff.
remove generated files from the source tree. python is required
to build now.
base/trace.hh:
no need for the underscore in the name
base/traceflags.py:
clean up code
--HG--
extra : convert_revision : f68af8c3460eb7e73a1defaea3081a02ad7db33c
Add support for generic visitors for stats and use them
to implement independent output functions.
Support for mysql output and some initial code for hacking
on mysql output with python
arch/alpha/pseudo_inst.cc:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/sat_counter.cc:
base/sat_counter.hh:
cpu/simple_cpu/simple_cpu.cc:
kern/tru64/tru64_events.cc:
sim/main.cc:
sim/process.cc:
sim/process.hh:
sim/sim_events.cc:
sim/sim_object.cc:
sim/system.hh:
update for changes in stats package
base/statistics.cc:
move the python output code to base/stats/puthon.(cc|hh)
and reimplement it as a visitor.
move the text output code to base/stats/text.(cc|hh) and
reimplement it as a visitor.
move the database stuff into base/stats/statdb.(cc|hh) and
get rid of the class. Put everything as globals in the
Statistics::Database namespace.
allocate unique ids for all stats.
directly implement the check routine and get rid of the
various dumping routines since they're now in separate files.
make sure that no two stats have the same name
clean up some loops
base/statistics.hh:
major changes to the statistics package again
lots of code was factored out of statistics.hh into several
separate files in base/stats/ (this will continue)
There are now two Stat package types Result and Counter that
are specified to allow the user to keep the counted type
separate from the result type. They are currently both doubles
but that's an experiment. There is no more per stat ability to
set the type. Statistics::Counter is not the same as Counter!
Implement a visitor for statistics output so that new output
types can be implemented independently from the stats package
itself.
Add a unique id to each stat so that it can be used to keep
track of stats more simply. This number can also be used in
debugging problems with stats.
Tweak the bucket size stuff a bit to make it work better.
fixed VectorDist size bug
cpu/memtest/memtest.cc:
Fix up for changes in stats package
Don't use value() since it doesn't work with binning. If you
want a number as a stat, and to use it in the program itself,
you really want two separate variables, one that's a stat,
and one that's not.
cpu/memtest/memtest.hh:
Fix up for changes in stats package
test/Makefile:
Try to build stuff now that directories matter
test/stattest.cc:
test all new output types
choose which one with command line options
--HG--
extra : convert_revision : e3a3f5f0828c67c0e2de415d936ad240adaddc89
