Commit graph

8551 commits

Author SHA1 Message Date
Ali Saidi
63eb337b3b ARM: Update stats for the previous changes and add ARM_FS/O3 regression. 2011-03-17 19:20:22 -05:00
Chris Emmons
ccaaa98b49 ARM: Add minimal ARM_SE support for m5threads.
Updated some of the assembly code sequences to use armv7 instructions and
coprocessor 15 for storing the TLS pointer.
2011-03-17 19:20:20 -05:00
Ali Saidi
53ab306acc ARM: Fix subtle bug in LDM.
If the instruction faults mid-op the base register shouldn't be written back.
2011-03-17 19:20:20 -05:00
Ali Saidi
4c7a7796ad ARM: Implement the Instruction Set Attribute Registers (ISAR).
The ISAR registers describe which features the processor supports.
Transcribe the values listed in section B5.2.5 of the ARM ARM
into the registers as read-only values
2011-03-17 19:20:20 -05:00
Ali Saidi
5480ec798a ARM: Identify branches as conditional or unconditional and direct or indirect. 2011-03-17 19:20:20 -05:00
Ali Saidi
887e9e2b99 ARM: Bare metal system should have 256MB of RAM. 2011-03-17 19:20:20 -05:00
Ali Saidi
b754ad85c0 ARM: Fix small bug with VLDM/VSTM instructions. 2011-03-17 19:20:20 -05:00
Ali Saidi
b78be240cf ARM: Detect and skip udelay() functions in linux kernel.
This change speeds up booting, especially in MP cases, by not executing
udelay() on the core but instead skipping ahead tha amount of time that is being
delayed.
2011-03-17 19:20:20 -05:00
Ali Saidi
fe3d790ac8 ARM: Allow conditional quiesce instructions.
This patch prevents not executed conditional instructions marked as
IsQuiesce from stalling the pipeline indefinitely. If the instruction
is not executed the quiesceSkip psuedoinst is called which schedules a
wakes up call to the fetch stage.
2011-03-17 19:20:20 -05:00
Ali Saidi
845f791f37 Stats: Update the statistics for rfe patch. 2011-03-17 19:20:20 -05:00
Matt Horsnell
031f396c71 ARM: Fix RFE macrop.
This changes the RFE macroop into 3 microops:

URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset;         // optionally auto-increment
PC = URa; CPSR = URb;     // write to the PC and CPSR.

Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.
2011-03-17 19:20:19 -05:00
Matt Horsnell
e65f480d62 ARM: Rename registers used as temporary state by microops. 2011-03-17 19:20:19 -05:00
Ali Saidi
799c3da8d0 O3: Send instruction back to fetch on squash to seed predecoder correctly. 2011-03-17 19:20:19 -05:00
Ali Saidi
30143baf7e O3: Cleanup the commitInfo comm struct.
Get rid of unused members and use base types rather than derrived values
where possible to limit amount of state.
2011-03-17 19:20:19 -05:00
Ali Saidi
db35053655 ARM: Previous change didn't end up setting instFlags, this does. 2011-03-17 19:20:19 -05:00
Ali Saidi
7112b44362 O3: Update regressions for mem block caching change. 2011-03-17 19:20:19 -05:00
Ali Saidi
a432d8e085 Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.
This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
2011-03-17 19:20:19 -05:00
Ali Saidi
2f40b3b8ae O3: Fix unaligned stores when cache blocked
Without this change the a store can be issued to the cache multiple times.
If this case occurs when the l1 cache is out of mshrs (and thus blocked)
the processor will never make forward progress because each cycle it will
send a single request using the recently freed mshr and not completing the
multipart store. This will continue forever.
2011-03-17 19:20:19 -05:00
Lisa Hsu
c4de6a0522 Ruby: minor bugfix, line did not adhere to some macro usage conventions. 2011-03-17 17:08:35 -07:00
Lisa Hsu
556b5c5488 Ruby: expose a simple mod function in slicc interface. 2011-03-17 17:01:41 -07:00
Ali Saidi
3a44307e94 X86: Update the stats for parser on x86 O3. 2011-03-17 00:43:54 -04:00
Gabe Black
27f5a8c812 X86: Update the stats for gzip on x86 O3. 2011-03-16 19:08:41 -07:00
Gabe Black
47615d06bd Regressions: Move the X86_FS regressions to "quick" instead of "long".
--HG--
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
2011-03-12 14:41:30 -08:00
Gabe Black
591b05cf02 Regressions: Make X86_FS run automatically. 2011-03-12 14:38:57 -08:00
Gabe Black
02f10fbdc8 SCons: Stop embedding the mercurial revision into the binary.
This causes a lot of rebuilds that could have otherwise possibly been
avoided, and, more annoyingly, a lot of unnecessary rerunning of the
regressions. The benefits of having the revision in the output haven't
materialized, so this change removes it.
2011-03-11 11:27:36 -08:00
Gabe Black
b6ba1a528b Gems: Eliminate the now unused GEMS_ROOT scons variable. 2011-03-11 11:27:26 -08:00
Gabe Black
a78e772929 Ruby: Get rid of the dead ruby tester.
None of the code in the ruby tester directory is compiled or referred to
outside of that directory. This change eliminates it. If it's needed in the
future, it can be revived from the history. In the mean time, this removes
clutter and the only use of the GEMS_ROOT scons variable.
2011-03-11 11:27:16 -08:00
Yi Xiang
d7b5508875 Alpha: Fix the datatypes of some values read from the simulated kernel. 2011-03-08 21:43:11 -08:00
Gabe Black
674b941282 SCons: Fix the polarity on the --ignore-style check. 2011-03-04 00:11:02 -08:00
Gabe Black
96e0f3bda5 SCons: Clean up some inconsistent capitalization in scons options. 2011-03-03 23:55:21 -08:00
Gabe Black
fa448129b1 SCons: Turn some scons variables into command line options. 2011-03-03 23:54:31 -08:00
Gabe Black
880edb0b59 Mips: MIPS_FS doesn't build currently, so delete it to avoid confusion.
MIPS_FS doesn't build and presumably doesn't work right now. Users might see
the MIP_FS file in build_opts and expect it to work. To avoid confusion, this
change deletes that file.
2011-03-03 23:01:38 -08:00
Gabe Black
441ab29820 Statetrace: Stub out the missing i386 version of sendState. 2011-03-02 22:53:11 -08:00
Gabe Black
9d2650792f Statetrace: Rename i386 to i686.
--HG--
rename : util/statetrace/arch/i386/tracechild.cc => util/statetrace/arch/i686/tracechild.cc
rename : util/statetrace/arch/i386/tracechild.hh => util/statetrace/arch/i686/tracechild.hh
2011-03-02 22:53:11 -08:00
Gabe Black
3bcd77ddef Statetrace: Fix the i686 detection macro. 2011-03-02 22:53:11 -08:00
Gabe Black
16d997840a Statetrace: Use sys/user.h instead of linux/user.h. 2011-03-02 22:53:11 -08:00
Gabe Black
d7a47af12d Statetrace: Tweak the help for the -nt option. 2011-03-02 22:53:11 -08:00
Gabe Black
eab89a09d2 Statetrace: Accomodate cross compiling statetrace with scons.
--HG--
rename : util/statetrace/arch/tracechild_amd64.cc => util/statetrace/arch/amd64/tracechild.cc
rename : util/statetrace/arch/tracechild_amd64.hh => util/statetrace/arch/amd64/tracechild.hh
rename : util/statetrace/arch/tracechild_arm.cc => util/statetrace/arch/arm/tracechild.cc
rename : util/statetrace/arch/tracechild_arm.hh => util/statetrace/arch/arm/tracechild.hh
rename : util/statetrace/arch/tracechild_i386.cc => util/statetrace/arch/i386/tracechild.cc
rename : util/statetrace/arch/tracechild_i386.hh => util/statetrace/arch/i386/tracechild.hh
rename : util/statetrace/arch/tracechild_sparc.cc => util/statetrace/arch/sparc/tracechild.cc
rename : util/statetrace/arch/tracechild_sparc.hh => util/statetrace/arch/sparc/tracechild.hh
rename : util/statetrace/tracechild_arch.cc => util/statetrace/base/arch_check.h
rename : util/statetrace/regstate.hh => util/statetrace/base/regstate.hh
rename : util/statetrace/statetrace.cc => util/statetrace/base/statetrace.cc
rename : util/statetrace/tracechild.cc => util/statetrace/base/tracechild.cc
rename : util/statetrace/tracechild.hh => util/statetrace/base/tracechild.hh
2011-03-02 22:53:11 -08:00
Gabe Black
9151c4039a Statetrace: Convert the build to scons. 2011-03-02 22:53:11 -08:00
Gabe Black
db090ea139 Statetrace: Allow the user to override CXX. 2011-03-02 22:53:11 -08:00
Gabe Black
43eda1f285 Statetrace: Get rid of explicit register name handling. 2011-03-02 22:53:10 -08:00
Gabe Black
3c19e45a68 Statetrace: Kill the printer functionality in statetrace. 2011-03-02 22:53:10 -08:00
Gabe Black
3df970f0de Statetrace: Clean up style. 2011-03-02 22:53:10 -08:00
Gabe Black
07b507d278 X86: Use the npc as the pc when doing a nativetrace, not what M5 considers the pc. 2011-03-02 00:41:44 -08:00
Gabe Black
8966312785 X86: Decode the mysterious and elusive ffreep x87 instruction.
The internet says this instruction was created by accident when an Intel CPU
failed to decode x87 instructions properly. It's been documented on a few rare
occasions and has generally worked to ensure backwards compatability. One
source claims that the gcc toolchain is basically the only thing that emits
it, and that emulators/binary translators like qemu and bochs implement it.

We won't actually implement it here since we're hardly implementing any other
x87 instructions either. If we were to implement it, it would behave the same
as ffree but then also pop the register stack.

http://www.pagetable.com/?p=16
2011-03-02 00:41:38 -08:00
Gabe Black
579c5f0b65 Spelling: Fix the a spelling error by changing mmaped to mmapped.
There may not be a formally correct spelling for the past tense of mmap, but
mmapped is the spelling Google doesn't try to autocorrect. This makes sense
because it mirrors the past tense of map->mapped and not the past tense of
cape->caped.

--HG--
rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh
rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh
rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh
rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh
rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh
rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh
2011-03-01 23:18:47 -08:00
Gabe Black
e8b982e247 X86: Update stats for the x86 o3 hello world regression. 2011-03-01 23:18:00 -08:00
Gabe Black
2e4fb3f139 X86: Mark IO reads and writes as non-speculative. 2011-03-01 22:42:59 -08:00
Gabe Black
72d35701e9 X86: Mark prefetches as such in their instruction and request flags. 2011-03-01 22:42:18 -08:00
Nilay Vaish
3a10b200f7 Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF()
has not been provided with correct number of arguments. The patch fixes these
bugs.
2011-03-01 15:26:11 -06:00