Commit graph

333 commits

Author SHA1 Message Date
Gabe Black
2c5e03550a Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh.
SConscript:
    Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh
    targetarch/isa_traits.hh is now included through arch/isa_traits.hh
    vptr.hh was removed from targetarch, and moved to sim
arch/alpha/pseudo_inst.cc:
    Moved vptr.hh from targetarch to sim
base/loader/object_file.hh:
base/loader/symtab.hh:
cpu/base.hh:
dev/ide_disk.cc:
    Changed the include of isa_traits.hh from targetarch to arch
cpu/static_inst.hh:
dev/platform.hh:
dev/simple_disk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/mbuf.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/process.hh:
sim/syscall_emul.hh:
    Changed the include of isa_traits.hh from targetarch to arch.
kern/linux/linux_threadinfo.hh:
    Changed the include of vptr.hh from targetarch to sim.
sim/byteswap.hh:
    Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t)
sim/vptr.hh:
    Fixed the assert in the equals operator.
    Changed the AlphaISA namespace reference to TheISA.
    Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures.
    Added an include of arch/isa_traits.hh so that TheISA would be defined.

--HG--
extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
2006-02-12 12:40:58 -05:00
Gabe Black
2939a7089a byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    Added the endianness namespace. This may change.
cpu/exec_context.hh:
    Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/o3/alpha_cpu.hh:
    Forced LittleEndianness, for lack of a better solution.
cpu/o3/alpha_cpu_impl.hh:
    Cleared away some commented out code.
cpu/o3/fetch_impl.hh:
    Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/simple/cpu.cc:
    Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine.
dev/disk_image.cc:
    Changed the include path of byteswap.hh
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
    Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution.
sim/system.cc:
    Forced LittleEndianness for lack of a better solution.

--HG--
extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206
2006-02-03 00:16:44 -05:00
Nathan Binkert
36373fa465 Virtualized SINIC fixes
dev/pktfifo.hh:
    we can't modify i because it's used further down to remove
    the packet from the fifo.  Instead, copy the iterator and
    modify that to get the previous packet.
dev/sinic.cc:
    - don't change the transmit state and kick the machine unless
    we're at the head of the txList.
    - add a couple of debugging statements to figure out how far
    along we've gotten in processing a packet.
    - assert that the current tx vnic has something to do when
    we start processing the state machine.

--HG--
extra : convert_revision : 588fe2c7d810be0e3d8d39c5cc0ec8a72119517e
2005-11-28 18:40:58 -05:00
Nathan Binkert
47ff0af17e Virtualize sinic
separate the rx thread and tx thread and get rid of the dedicated flag.

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
python/m5/objects/Ethernet.py:
    dedicated flag goes away, we have new individual flags for
    rx thread and tx thread
dev/sinic.cc:
    Virtualize sinic
    - The io registers are replicated many times in memory, allowing the NIC to
    differentiate among several virtual interfaces.
    - On the TX side, this allows multiple CPUs to initiate transmits at the same
    time without locking in the software.  If a partial packet is transmitted,
    then the state machine blocks waiting for that virtual interface to complete
    its packet.  Then the state machine will move on to the next virtual
    interface.  The commands are kept in fifo order.
    - On the RX side, multiple partial transmits can be simultaneously done.
    Though a packet does not deallocate its fifo space until all preceeding
    packets in the fifo are deallocated.  To enable multiple receives, it
    is necessary for each virtual nic to keep its own information about its
    progress through the state machine.
dev/sinic.hh:
    Virtualize sinic
    Receive state must be virtualized since we allow the receipt of packets in
    parallel.
dev/sinicreg.hh:
    Virtualize sinic
    separate rx thread and tx thread
    create a soft interrupt and add a command to trigger it.
    pad out the reserved bits in the RxDone and TxDone regs

--HG--
extra : convert_revision : c10bb23a46a89ffd1e08866c1f1621cb98069205
2005-11-25 13:33:36 -05:00
Nathan Binkert
60e92986f7 Add the capability to iterate through the packets in a pktfifo,
and to remove elements in the middle of the fifo.  These elements
do not free space, they are just marked removed.  Space is only
freed from the front of the fifo.

dev/etherpkt.cc:
    serialize the current slack
dev/etherpkt.hh:
    add "slack" to the ethernet packet.  It is to be used by any fifo that
    the packet is currently in to account for extra space that the packet
    may be occupying due to the fifo organization.

--HG--
extra : convert_revision : 8e7c541ba316a9a76495c54cc5f707f8fc65b6d5
2005-11-25 11:22:41 -05:00
Nathan Binkert
fb3ae7264f add the cpu number of the request to various panic and trace
output for sinic

dev/sinic.cc:
    add the cpu number of the request to various panic and trace
    output

--HG--
extra : convert_revision : e778a5c925e194652bec47af678488acf48c1ae0
2005-11-22 00:17:05 -05:00
Nathan Binkert
f806a25c9e add support for delaying pio writes until the cache access occurs
dev/ns_gige.cc:
    add support for delaying pio writes until the cache access occurs
    the only write we delay are for CR_TXE and CR_RXE
dev/sinic.cc:
dev/sinic.hh:
    the txPioRequest and rxPioRequest things were more or less bogus
    add support for delaying pio writes until the cache access occurs
dev/sinicreg.hh:
    Add delay_read and delay_write to the register information struct
    for now, we won't delay any reads, and we'll delay the writes that
    initiate DMAs
python/m5/objects/Ethernet.py:
    add a parameter to delay pio writes until the timing access
    actually occurs.

--HG--
extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d
2005-11-21 23:43:15 -05:00
Nathan Binkert
2b76b41b90 have sinic use the new readBar/writeBar stuff that's in the
pci device base class

dev/sinic.cc:
dev/sinic.hh:
    use the new readBar/writeBar stuff that's in the pci device
    base class

--HG--
extra : convert_revision : 8a0b2bde3cc13597785d6ea75d6e6811680bb01b
2005-11-21 21:52:04 -05:00
Nathan Binkert
48863a1a43 Add a bunch of functions to manage the BAR addresses. This
makes it easier to implement PCI device models.

dev/pcidev.cc:
    default implementations for read/write and readBarX/writeBarX functions

--HG--
extra : convert_revision : bbe2e2a2a506e2dd94d98f8e0feaefef96380be9
2005-11-21 00:38:53 -05:00
Nathan Binkert
12d903a650 io_bus is split out into pio_bus and dma_bus so that any device
can specify either independently.

python/m5/objects/Device.py:
    io_bus is split out into pio_bus and dma_bus so that any device
    can specify either independently.
    dma_bus defaults to point to whatever pio_bus uses.

--HG--
extra : convert_revision : d35d5374d0bf592f6b5df465c05203577b8b8763
2005-11-20 16:57:53 -05:00
Ali Saidi
60480de7c3 Update random come to always have explict min/max
--HG--
extra : convert_revision : a2d1f6f8aa1df24ea524792f687f4d3ee31101f0
2005-11-11 18:41:45 -05:00
Ali Saidi
f0ee50c32f Don't call Random.uniform() unnecessarily
--HG--
extra : convert_revision : 82b092391f7c866f33ddb028070181038bdce0f8
2005-11-02 15:29:08 -05:00
Ali Saidi
3b66cb49ec Merge zizzer:/bk/m5
into  zeep.eecs.umich.edu:/z/saidi/work/m5

--HG--
extra : convert_revision : 3cc23080d19cc464a8ba7c1c93b6e5d45af7d463
2005-11-02 14:56:18 -05:00
Ali Saidi
07ef1170e0 Add ability to slightly perturb latency of ethernet/memory
base/random.cc:
    Change normal random function to Xrand48 so we have one source of
    randomness for everything.
base/random.hh:
    Add uniform distribution ability to random functions
dev/etherlink.cc:
dev/etherlink.hh:
    Add ability to slightly perturb latency of ethernet

--HG--
extra : convert_revision : f7f856761fd525c233ae2a6d993b1fd702b488f7
2005-11-02 14:47:37 -05:00
Nathan Binkert
b7b8ffa7b7 Major changes to sinic device model. Rearrage read/write, better
interrupts.

dev/sinic.cc:
    - The prepareRead function sets all the variables in the register
    file that depend on various state bits that change on the fly.
    Includes RxDone, RxWait, TxDone, and TxWait
    - Use the new register information accessor functions to grab
    validity and size information for the read and write functions
    - read all registers directly from the register space by offset
    and size, not by actual name (less code)
    - The side effect of reading the interrupt status (clearing it) now
    happens outside the actual chunk of code where the value is loaded.
    - Add an iprRead function for when we may want speculative access
    to device registers through an ipr or special instruction.
    - When RxData or TxData are written, their busy flag is set to
    indicate that they have an outstanding transaction.
    - The RxHigh and TxLow interrupts are special, they only interrupt
    if the rxEmpty or txFull limits were hit
    - Move reset to the command register
    - Update more registers on reset, clear rxEmpty and txFull
    - Data dumps only happen if EthernetData trace flag set
    - When a DMA completes, kick the other engine if it was waiting
    - implement all of the new interrupts
    - serialize the new stuff
dev/sinic.hh:
    - Put all registers with their proper size and alignment into
    the regs struct so that we can copy multiple at a time.
    - Provide accessor functions for accessing the registers with
    different sizes.
    - Flags to track when the rx fifo hit empty and the tx fifo became
    full.  These flags are used to determine what to do when below
    the watermarks, and are reset when crossing the watermark.
    - the txDmaEvent should actually trigger the txDmaDone function
    - Add an iprRead function for when we may want speculative access
    to device registers through an ipr or special instruction.
    - The prepareRead function sets all the variables in the register
    file that depend on various state bits that change on the fly.
    - add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
    Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
    rename XxThreshold to XxFifoMark
    Move Reset to the Command register
    Add Thread to the Config register
    New interrupts, better names
    More info in RxDone and TxDone
    Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
    Both sinic and nsgige have the dedicated thread
    Add a parameter to configure the maximum number for receive
    packets per interrupt

--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-21 20:28:21 -04:00
Nathan Binkert
ad2ff26c66 missed another pio interface name
dev/sinic.cc:
    better name for both pio interfaces

--HG--
extra : convert_revision : f7821c9c28b0095b366177b4c48a4ec14c3c89ee
2005-10-21 19:38:02 -04:00
Nathan Binkert
cf95624e92 better naming for pio interfaces
dev/ns_gige.cc:
    why call it pio2 when there's only one?
dev/sinic.cc:
    Give the interface a different name for stats/output purposes

--HG--
extra : convert_revision : 895732f1a7e4c53e058a42b51320c2115dc05638
2005-10-21 19:35:49 -04:00
Nathan Binkert
a51565f6ae It's not necessary for a device to call recvDone, that
automatically happens in the interface after the packet
is delivered to the device.

--HG--
extra : convert_revision : 07890c4c5ce83fe709ce203f66c330d7cd631235
2005-10-21 19:18:19 -04:00
Nathan Binkert
2badc0113c Shuffle around device names to make things easier to read.
Create EtherDevBase which both Sinic and NSGigE derive from
bump fifos
drop rx max copy size to 1514 bytes to be friendlier with linux
default interrupt delay is 10us

dev/ns_gige.cc:
    Shuffle around parameters to make it easier to find stuff
dev/sinic.cc:
    Shuffle around parameters to make it easier to find stuff
    rename cycleTime -> clock
dev/sinic.hh:
    rename cycleTime -> clock

--HG--
extra : convert_revision : a673bee875e50d083098991aea20972fa8d5b5c7
2005-10-18 22:05:05 -04:00
Nathan Binkert
4f43bc65ea use the dedicated flag, no more exposing the m5reg directly
dev/ns_gige.cc:
    stop exposing the m5reg to the configuration stuff and build it
    based on exposed flags.  Expose dedicated now.
dev/ns_gige.hh:
    goodbye m5reg hello dedicated
dev/ns_gige_reg.h:
    Flags for the M5REG

--HG--
extra : convert_revision : 11134fe67cdf5291caacf9b3041739c437b983e3
2005-10-18 21:01:05 -04:00
Nathan Binkert
17b1c8f90d better english in stat descriptions for NS GigE
dev/ns_gige.cc:
    better english in stat descriptions

--HG--
extra : convert_revision : e75fc71e3285389cd38a9a00376a494778536b1d
2005-10-12 13:53:10 -04:00
Nathan Binkert
80a5c93036 Add support for 64-bit addresses to the NS GigE device model.
dev/ns_gige.cc:
    Add support for 64-bit addresses
dev/ns_gige.hh:
dev/ns_gige_reg.h:
    Need both cached 32-bit and 64-bit descriptors

--HG--
extra : convert_revision : 514788d8d95554b3512f1b75db5314c823453a8c
2005-10-12 13:39:40 -04:00
Ali Saidi
5f7952f8e1 fix for delayed state machine changes
--HG--
extra : convert_revision : db19e3687f48799725a9062e014588d318988cee
2005-09-29 17:09:53 -04:00
Steve Reinhardt
6637874225 Fix IDE disk UDMA mode support mask to actually reflect support for
modes 4 *and below*, not just mode 4.

dev/ide_disk.cc:
    Fix UDMA mode support mask to actually reflect support for
    modes 4 *and below*, not just mode 4.

--HG--
extra : convert_revision : 3506d503a5e8ce8a8686fb3a552383d365be0d41
2005-09-24 15:22:28 -04:00
Nathan Binkert
e1c61e5b2f Tweak the set of coalesced interrupts
dev/ns_gige.cc:
    clean up usage of ISR_FOO macros
dev/ns_gige_reg.h:
    Clean up #defines
    make ISR_RXIDLE and ISR_TXIDLE coalesced

--HG--
extra : convert_revision : fd64fc6a441d096fc45737fdcb837de8868ca10a
2005-09-18 21:22:57 -04:00
Nathan Binkert
f88d7c7456 Fix the EtherDump parameters
dev/etherdump.cc:
    no default parameters anymore they should be in python
python/m5/objects/Ethernet.py:
    move the maxlen parameter for EtherDump into python

--HG--
extra : convert_revision : a796353a68907dfeb22059cd3ad536e6e8f60998
2005-09-17 10:47:16 -04:00
Ali Saidi
d4de2ba0b4 only set an approriately sized piece of data. so break where appropriate
Again... how did this work?

--HG--
extra : convert_revision : 06dcab4ac9f5760c9847d0fa47fea67c4a46544a
2005-09-12 22:53:57 -04:00
Ali Saidi
c62760e3cb fixes for gcc 4.0
base/mysql.hh:
    include mysql_version to get rid of that annoying mysql error.
    make sure refcount is set in all constructors
base/pollevent.hh:
dev/ethertap.hh:
dev/pciconfigall.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
sim/param.cc:
    fix for gcc 4

--HG--
extra : convert_revision : be626af2f40ca402818996ef27249ae256c63ef1
2005-09-12 03:01:43 -04:00
Nathan Binkert
c761aaae65 Lots of fixes to serialization and naming of various device
objects.  The improper serialization of arrays was particularly
bad.

dev/alpha_console.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    the pio interface is a different simobject and should have a
    different name.
dev/ethertap.cc:
    fix serialization.
dev/ide_ctrl.cc:
    - the pio interface is a different simobject and should have a
    different name.
    - properly initialize variables
    - When serializing an array, the size is the number of elements,
    not the number of bytes!
dev/pcidev.cc:
    When serializing an array, the size is the number of elements,
    not the number of bytes!
dev/tsunami_io.hh:
    Don't make objects SimObjects if they're not exposed to python.
    Don't add serialization functions to events, it's generally not
    what you want.
    allow the real time clock and interval timer to serialize themselves,
    must pass a base name since it is not a SimObject and the values will
    be going into the section of the parent.

--HG--
extra : convert_revision : 3fc5de9b858ed770c8f385cf38b53242cf859c33
2005-08-23 11:45:52 -04:00
Nathan Binkert
1771ee203f don't use sprintf. It's not guaranteed to not scribble over memory.
base/remote_gdb.cc:
    use snprintf, it's safer
dev/ide_disk.cc:
    use strncpy instead of snprintf

--HG--
extra : convert_revision : 90455e3f6bcb4c771724298a5a0b79a5b483a85c
2005-08-23 11:38:27 -04:00
Steve Reinhardt
03e256b0f0 A few minor fixes to get things to build on Cygwin.
README:
    Clarify cygwin EIO error explanation.
build/SConstruct:
    Cygwin header files cause uninitialized var warnings.
dev/ide_ctrl.cc:
    Get rid of unnecessary byte-swap calls, some of which were
    too ambiguous for cygwin (or gcc 3.4.4).
dev/pcidev.cc:
    Disambiguate arg for overloaded byte swap operation
    (and fix it to be the correct one).

--HG--
extra : convert_revision : be37c6315aacbec6332b1d09e726b39b4aa18dce
2005-08-19 17:10:17 -04:00
Nathan Binkert
4f53a4705e Fix a couple of turbolaser problems that were introduced by the
new freebsd code.

dev/ns_gige.cc:
    g++ doesn't like it when you declare a variable inside a case
    label.  Pull the declaration outside.

--HG--
extra : convert_revision : d39e84fc58f2dd5b09c5948eedb4b1d7848e9817
2005-08-18 13:29:40 -04:00
Benjamin Nash
979d609656 Merge zed.eecs.umich.edu:/.automount/fox/y/mserrano/m5_dir/m5
into  zed.eecs.umich.edu:/z/benash/bk/m5

--HG--
extra : convert_revision : 9b7ca872187a13179118ad0651301d531332dc63
2005-08-16 15:45:30 -04:00
Miguel Serrano
1906abcde0 Uart fix.
dev/uart8250.cc:
    Fixed implementation of "transmit interrupt clear".

--HG--
extra : convert_revision : cb69d61413ea799d5d3825fe2f0891dd72995561
2005-08-16 15:44:57 -04:00
Benjamin Nash
bcc333e920 Merge zed.eecs.umich.edu:/.automount/fox/y/mserrano/m5_dir/m5
into  zed.eecs.umich.edu:/z/benash/bk/m5

dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/rtcreg.h:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/uart8250.cc:
dev/uart8250.hh:
python/m5/objects/Tsunami.py:
    Merge code.

--HG--
extra : convert_revision : e97d5dbcc051d2061622201265430d359f995d48
2005-08-15 17:17:17 -04:00
Miguel Serrano
b64eae5e52 Changes for getting FreeBSD to run.
SConscript:
    Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
    Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
    Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
    Replaced htoa() with gtoh().
dev/disk_image.cc:
    Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
    Got rid of magic numbers.
    Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
    Got rid of unnecessary macros.
    Changed RegType_t to IdeRegType.
    Changed bmi_regs to allow accessing registers by name instead of just by array index.
    Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
    Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
    Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
    Made ReadConfig and WriteConfig begin with a lower-case letter.
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
    Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
    Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
    Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
    Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
    The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
    Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
    Added classes for RTC and PIT modules.
dev/tsunamireg.h:
    Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
    Got rid of a magic number.
    Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
    Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
    Replaced htoa() with htog().
python/m5/objects/Pci.py:
    PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
    TsunamiFake was renamed as IsaFake.
sim/system.cc:
    Replaced htoa()s with htog()s.
dev/isa_fake.cc:
    New BitKeeper file ``dev/isa_fake.cc''
    TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
    New BitKeeper file ``dev/isa_fake.hh''
    TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
    New BitKeeper file ``dev/pitreg.h''
    Useful macros for working with PIT (Periodic Interval Timer) registers.

--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
2005-08-15 16:59:58 -04:00
Benjamin Nash
49063eb24f Improve FreeBSD networking support.
dev/ns_gige.cc:
    Added FreeBSD support.  Required additional register read/write functionality, hash filtering (faked), and EEPROM read access.
dev/ns_gige.hh:
    Added constants and variables for FreeBSD support.  Also created eepromKick() to advance state machine.
dev/ns_gige_reg.h:
    Defined additional register bit fields.
dev/pcidev.cc:
    Fix &= typo.
dev/sinic.cc:
    Remove an INIT_PARAM_DFLT macro.
dev/tsunami_io.cc:
    Fix DPRINTF typo.
kern/freebsd/freebsd_system.cc:
    Edit comments.

--HG--
extra : convert_revision : 37aaa1303d57d3784381e85acb3bc1743adeb8c0
2005-08-12 18:30:35 -04:00
Benjamin Nash
a115249eb0 Merge zed.eecs.umich.edu:/.automount/fox/y/mserrano/m5_new/m5
into  zed.eecs.umich.edu:/z/benash/bk/m5

SConscript:
dev/ide_disk.hh:
    Formatting.
dev/ide_ctrl.cc:
    Endianness
dev/ide_disk.cc:
dev/pcidev.cc:
dev/tsunami_io.cc:
dev/uart8250.cc:
    Clean up code.

--HG--
extra : convert_revision : cb554f0e3a701371d2106cd7e11a4a22f773acc2
2005-07-28 13:16:45 -04:00
Miguel Serrano
74fd4f68c5 .
SConscript:
    add pcifake
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
    endianess
dev/tsunami_io.cc:
    rtc, date/time

--HG--
extra : convert_revision : 21ad27c780749cb6f6eef2b57798c0c292c3f14d
2005-07-28 11:49:01 -04:00
Miguel Serrano
6a8ae7a6a0 ghgfsdf
dev/pciconfigall.cc:
    removed union.
dev/pcidev.cc:
    .
dev/rtcreg.h:
    more macros to avoid magic numbers.
dev/tsunami_io.cc:
    replaced magic numbers, no more advancing RTC as it isn't reaaly necessary.
dev/tsunami_io.hh:
    removed declarations of things that go unused.
dev/uart8250.cc:
    reading the Interrupt ID register should clear TX interrupt flag.
dev/uart8250.hh:
    useful #defines.
kern/freebsd/freebsd_system.cc:
kern/freebsd/freebsd_system.hh:
    nothing.
python/m5/objects/Pci.py:
    new PciFake.

--HG--
extra : convert_revision : 88259704f5b215591d1416360180810fcda14d26
2005-07-28 11:47:06 -04:00
Benjamin Nash
6e0ad62fdc Various changes to I/O, addition of PciFake device to improve FreeBSD compatibility.
SConscript:
    Include pcifake.cc, fix spacing.
dev/ide_ctrl.cc:
    Consolidate switch-case blocks.
dev/ide_disk.cc:
    Add comments.
dev/pciconfigall.cc:
    Adjust spacing.
dev/pcidev.cc:
    Adjust spacing, rearrange code.
dev/tsunami_io.cc:
    Rearrange code.
dev/uart8250.cc:
    Switch uart interrupt interval back to original value.
python/m5/objects/Pci.py:
    Add PciFake class to be used as a PCI-ISA bridge device.

--HG--
extra : convert_revision : 8aea94318510079a310377f297aa161ba5f7864c
2005-07-26 12:28:33 -04:00
Benjamin Nash
32b52fe712 Various changes to m5/dev files to work with FreeBSD.
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/pcidev.cc:
    Made endian-independent.
dev/ide_disk.hh:
    fixed.
dev/pciconfigall.cc:
    The data to write is contained in a 32-bit unsigned int now. The union method would not have worked on big-endian machines.
dev/pcidev.hh:
    Fixed typo.
dev/tsunami_io.cc:
    Return zero on RTC alarm reads.
dev/uart8250.cc:
    Fix uart interrupt handling.

--HG--
extra : convert_revision : b5c08e8e77644c399c20888666406805ff1b6649
2005-07-13 12:30:13 -04:00
Benjamin Nash
6d7911dea0 Hand merge ide_disk.cc
dev/ide_disk.cc:
    Don't initialize data to 0.

--HG--
extra : convert_revision : 643bcf15b52c3e14231d8136b8cb049a8896457a
2005-07-01 15:57:14 -04:00
Miguel Serrano
4f2480a18b Merge m5read@m5.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/.automount/fox/y/mserrano/m5_new/m5

--HG--
extra : convert_revision : bb3e977e79599c459fb32f309ce5b486f1639afa
2005-07-01 15:12:09 -04:00
Miguel Serrano
16a2357e86 .
--HG--
extra : convert_revision : 1ed206b27498641b64d7f35c74ea1f0623398d4e
2005-07-01 15:10:18 -04:00
Benjamin Nash
6bf9703213 Merge m5read@m5.eecs.umich.edu:/bk/m5
into zed.eecs.umich.edu:/z/benash/bk/m5

--HG--
extra : convert_revision : b421397b21326ec2bdd3ce82b9f69e224b380610
2005-07-01 15:07:13 -04:00
Benjamin Nash
81b57af241 Fix formatting, move default size (0x8) of TsunamiFake from C++ code to Python code.
dev/ide_disk.cc:
    Fix formatting.  Panic if unexpected register type is given.
python/m5/objects/Tsunami.py:
    Add default size of TsunamiFake device.

--HG--
extra : convert_revision : 03a35a2f6468b95746cba41ce7e93afeeb70ccef
2005-07-01 13:06:35 -04:00
Benjamin Nash
e563acd5c6 Formatting, reduce maximum number of functional memory children.
dev/ide_disk.cc:
dev/pcidev.cc:
    Formatting.

--HG--
extra : convert_revision : 6f5824aa220fe311751fb10ec8648fe64dfa4775
2005-06-30 13:12:12 -04:00
Steve Reinhardt
5107b3bc83 Fixes for cygwin compile.
dev/ide_atareg.h:
    Need endian.h for LITTLE_ENDIAN.
sim/syscall_emul.hh:
    Need to include sys/fcntl.h to get O_BINARY.

--HG--
extra : convert_revision : 606f9506dc483f3952dcc65b8ba25c28001f2c43
2005-06-30 00:42:27 -04:00
Nathan Binkert
451e41c6e9 Fix uninitialized variables in ide controller
dev/ide_ctrl.cc:
    Initialize variables to zero to avoid uninitialized usage.

--HG--
extra : convert_revision : 98fd0bfc2b7530938c6ab3a55345d0e594098238
2005-06-29 22:16:40 -04:00