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Nathan Binkert f806a25c9e add support for delaying pio writes until the cache access occurs 
dev/ns_gige.cc:
    add support for delaying pio writes until the cache access occurs
    the only write we delay are for CR_TXE and CR_RXE
dev/sinic.cc:
dev/sinic.hh:
    the txPioRequest and rxPioRequest things were more or less bogus
    add support for delaying pio writes until the cache access occurs
dev/sinicreg.hh:
    Add delay_read and delay_write to the register information struct
    for now, we won't delay any reads, and we'll delay the writes that
    initiate DMAs
python/m5/objects/Ethernet.py:
    add a parameter to delay pio writes until the timing access
    actually occurs.

--HG--
extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d
2005-11-21 23:43:15 -05:00
..
alpha_access.h Don't hard code the location of m5AlphaAccess. Instead, move the 2005-06-28 12:42:15 -04:00
alpha_console.cc io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
alpha_console.hh io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
baddev.cc io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
baddev.hh Many files: 2005-06-05 05:16:00 -04:00
disk_image.cc Changes for getting FreeBSD to run. 2005-08-15 16:59:58 -04:00
disk_image.hh Many files: 2005-06-05 05:16:00 -04:00
etherbus.cc Many files: 2005-06-05 05:16:00 -04:00
etherbus.hh Many files: 2005-06-05 05:16:00 -04:00
etherdump.cc Fix the EtherDump parameters 2005-09-17 10:47:16 -04:00
etherdump.hh Many files: 2005-06-05 05:16:00 -04:00
etherint.cc Many files: 2005-06-05 05:16:00 -04:00
etherint.hh Many files: 2005-06-05 05:16:00 -04:00
etherlink.cc Update random come to always have explict min/max 2005-11-11 18:41:45 -05:00
etherlink.hh Add ability to slightly perturb latency of ethernet/memory 2005-11-02 14:47:37 -05:00
etherpkt.cc Many files: 2005-06-05 05:16:00 -04:00
etherpkt.hh Many files: 2005-06-05 05:16:00 -04:00
ethertap.cc Lots of fixes to serialization and naming of various device 2005-08-23 11:45:52 -04:00
ethertap.hh fixes for gcc 4.0 2005-09-12 03:01:43 -04:00
ide_atareg.h Fixes for cygwin compile. 2005-06-30 00:42:27 -04:00
ide_ctrl.cc io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
ide_ctrl.hh io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
ide_disk.cc Fix IDE disk UDMA mode support mask to actually reflect support for 2005-09-24 15:22:28 -04:00
ide_disk.hh Changes for getting FreeBSD to run. 2005-08-15 16:59:58 -04:00
ide_wdcreg.h Fix doxgyen comments 2005-06-04 23:56:53 -04:00
io_device.cc Many files: 2005-06-05 05:16:00 -04:00
io_device.hh Many files: 2005-06-05 05:16:00 -04:00
isa_fake.cc io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
isa_fake.hh io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
ns_gige.cc add support for delaying pio writes until the cache access occurs 2005-11-21 23:43:15 -05:00
ns_gige.hh add support for delaying pio writes until the cache access occurs 2005-11-21 23:43:15 -05:00
ns_gige_reg.h use the dedicated flag, no more exposing the m5reg directly 2005-10-18 21:01:05 -04:00
pciconfigall.cc io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
pciconfigall.hh io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
pcidev.cc Add a bunch of functions to manage the BAR addresses. This 2005-11-21 00:38:53 -05:00
pcidev.hh Add a bunch of functions to manage the BAR addresses. This 2005-11-21 00:38:53 -05:00
pcireg.h Changes for getting FreeBSD to run. 2005-08-15 16:59:58 -04:00
pitreg.h Changes for getting FreeBSD to run. 2005-08-15 16:59:58 -04:00
pktfifo.cc Many files: 2005-06-05 05:16:00 -04:00
pktfifo.hh Many files: 2005-06-05 05:16:00 -04:00
platform.cc Many files: 2005-06-05 05:16:00 -04:00
platform.hh Many files: 2005-06-05 05:16:00 -04:00
rtcreg.h Changes for getting FreeBSD to run. 2005-08-15 16:59:58 -04:00
simconsole.cc Many files: 2005-06-05 05:16:00 -04:00
simconsole.hh Many files: 2005-06-05 05:16:00 -04:00
simple_disk.cc Many files: 2005-06-05 05:16:00 -04:00
simple_disk.hh Many files: 2005-06-05 05:16:00 -04:00
sinic.cc add support for delaying pio writes until the cache access occurs 2005-11-21 23:43:15 -05:00
sinic.hh add support for delaying pio writes until the cache access occurs 2005-11-21 23:43:15 -05:00
sinicreg.hh add support for delaying pio writes until the cache access occurs 2005-11-21 23:43:15 -05:00
tsunami.cc Fix minor doxygen issues. 2005-06-05 08:08:29 -04:00
tsunami.hh Fix minor doxygen issues. 2005-06-05 08:08:29 -04:00
tsunami_cchip.cc io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
tsunami_cchip.hh io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
tsunami_io.cc io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
tsunami_io.hh io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
tsunami_pchip.cc io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
tsunami_pchip.hh io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
tsunamireg.h Merge zed.eecs.umich.edu:/.automount/fox/y/mserrano/m5_dir/m5 2005-08-15 17:17:17 -04:00
uart.cc Many files: 2005-06-05 05:16:00 -04:00
uart.hh Many files: 2005-06-05 05:16:00 -04:00
uart8250.cc io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
uart8250.hh io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00