Commit graph

11680 commits

Author SHA1 Message Date
Dylan Johnson
eac27759e7 arm: Refactor aarch64 table walk logic to remove redundancy
The functional case is already handled within the fetchDescriptor()
function. We can thus use that function for both atomic and functional
mode when we start the table walk.

Change-Id: Iacaed28cd9024d259fd37a58150efd00ff94d86e
2016-08-02 10:38:02 +01:00
Dylan Johnson
f9a6f68e0b arm: Add check to fault routing for hypervisor/virtualization
This patch adds the option for faults to be routed to the hypervisor
using the pre-existing routeToHyp() functions that are present in each
fault type.

Change-Id: I9735512c094457636b9870456a5be5432288e004
2016-08-02 10:38:02 +01:00
Dylan Johnson
fc6879097b arm: Fix EL perceived at TLB for address translation instructions
During address translation instructions (such as AT S1E1R_Xt) the exception
level can be different than the current exception level. This patch fixes
how the TLB determines what EL to use during these instructions.

Change-Id: Ia9ce229404de9e284bc1f7479fd2c580efd55f8f
2016-08-02 10:38:02 +01:00
Dylan Johnson
2950a95672 arm: Add AArch64 hypervisor call instruction 'hvc'
This patch adds the AArch64 instruction hvc which raises an exception
from EL1 into EL2. The host OS uses this instruction to world switch
into the guest.

Change-Id: I930ee43f4f0abd4b35a68eb2a72e44e3ea6570be
2016-08-02 10:38:02 +01:00
Dylan Johnson
c53a57f74f arm: add stage2 translation support
Change-Id: I8f7c09c7ec3a97149ebebf4b21471b244e6cecc1
2016-08-02 10:38:02 +01:00
Curtis Dunham
49538a7118 arm: enable EL2 support
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
2016-08-02 10:38:01 +01:00
Dylan Johnson
4fbf40daab arm: invalidate TLB miscreg cache on modification of HSCTLR
Change-Id: I5212c91c56435fe008950ed99feacc6921609226
2016-08-02 10:38:01 +01:00
Dylan Johnson
e727a0eeaa arm: change instruction classes to catch hyp traps
Change-Id: I122918d0e3dfd01ae1a4ca4f19240a069115c8b7
2016-08-02 10:38:01 +01:00
Andreas Sandberg
c20b6c56f6 tests: Add regex-based ignore rules for ref files
There are cases where we need to ignore files with specific extensions
(e.g., when Mercurial litters the file system with patch
rejects). Implement this functionality using a helper class
(FileIgnoreList) that supports both regular expressions and basic
string comparisons.

Change-Id: I34549754bd2e10ed230ffb2dc057403349f8fa78
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-07-22 15:24:20 +01:00
Curtis Dunham
84f138ba96 stats: update references 2016-07-21 17:19:18 +01:00
Gabor Dozsa
a288c94387 arm, config: Add an example ARM big.LITTLE(tm) configuration script
An ARM big.LITTLE system consists of two cpu clusters: the big
CPUs are typically complex out-of-order cores and the little
CPUs are simpler in-order ones. The fs_bigLITTLE.py script
can run a full system simulation with various number of big
and little cores and cache hierarchy. The commit also includes
two example device tree files for booting Linux on the
bigLITTLE system.

Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-07-21 17:19:16 +01:00
Mitch Hayenga
752f1c1fe9 cpu: Fix Minor SMT WFI/drain interaction issues
The behavior of WFI is to cause minor to cease evaluating
pipeline logic until an interrupt is observed, however
a user may wish to drain the system while a core is sleeping
due to a WFI.  This patch makes WFI drain.  If an actual
drain occurs during a WFI, the CPU is already drained and will
immediately be ready for swapping, checkpointing, etc.  This
should not negatively impact performance as WFI instructions
are 'stream-changing' (treated like unpredicted branches), so
all remaining instructions are wrong-path and will be squashed
rapidly.

Change-Id: I63833d5acb53d8dde78f9f0c9611de0ece385e45
2016-07-21 17:19:16 +01:00
Mitch Hayenga
ff4009ac00 cpu: Add SMT support to MinorCPU
This patch adds SMT support to the MinorCPU.  Currently
RoundRobin or Random thread scheduling are supported.

Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
2016-07-21 17:19:16 +01:00
Mitch Hayenga
8a476d387c isa: Modify get/check interrupt routines
Make it so that getInterrupt *always* returns an interrupt if
checkInterrupts() returns true.  This fixes/simplifies handling
of interrupts on the SMT FS CPUs (currently minor).
2016-07-21 17:19:15 +01:00
David Guillen Fandos
d25b58036a base: Add total() to Vector2D stat
This patch adds a total() function to the Vector2D
stat type. Similar to other stats such as Scalar or
Vector it is useful to be able to read the total for
a given stat.
2016-07-21 17:19:15 +01:00
David Guillen Fandos
0020662459 mem: Add snoop traffic statistic 2016-07-21 17:19:14 +01:00
Jakub Jermar
86a25bbcee config: Allow SPARC FS image to be specified on the command line
At the moment the SPARC FS machine configuration comes with a hardcoded
value for using the Solaris 10 disk image from the OpenSPARC tarball. The
--disk-image option is completely ignored for SPARC. This simple patch
modifies the behavior so that --disk-image option is both taken into
account and also required. This makes it possible to easily change SPARC FS
images without having to modify the configuration files.
2016-07-19 09:52:46 -05:00
Mohammad Alian
c7bf0e9cdd dev, dist: Fixed a scheduling bug in the etherswitch
This patch fixes a bug in etherswitch. When a packet gets inserted
in the output fifo, the txEvent has to always be reschedule,
not only when an event is already scheduled. This can raise
the assertion in the reschedule function.
2016-07-19 09:48:56 -05:00
Andreas Sandberg
e9d0f6db88 base: Fix inverted check in ELF .text size warning 2016-07-11 16:30:35 +01:00
Andreas Sandberg
f471cc22f0 arm: Don't consult the TLB test iface for functional translations
Don't consult the TLB test interface for PA's returned by functional
translations by the AT instruction. We implement this by chaning the
ISA code to synthesize 0-length functional reads for the TLB lookup.
The TLB then bypasses the final PA check in the tester if the size is
zero.

Change-Id: I2487b7f829cea88c37e229e9fc7a4543aced961b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-07-11 10:39:56 +01:00
Andreas Sandberg
30cae3c213 base: Convert ELF .text size check assertion to a warning
The ELF loader currently has an assertion that checks if the size of a
loaded .text secion is non-zero. This is useful in the general case as
an empty text section normally indicates that there is something
strange with the ELF file. However, asserting isn't very useful. This
changeset converts the assert into a warning that tells the user that
something strange is happening.

Change-Id: I313e17847b50a0eca00f6bd00a54c610d626c0f0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-07-11 10:39:30 +01:00
Nikos Nikoleris
f4cc3a4d20 mem: Remove stale argument from a DPRINTF in the cache code
Change-Id: I70dd11c23b45dfc606ef08233d2e50fcc0817505
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-07-11 10:39:22 +01:00
Jason Lowe-Power
7c291677a8 misc: merge with sytle checker fix
Oops.
2016-07-01 10:37:57 -05:00
Matthew Poremba
134824e847 ruby: Fix double statistic registration in garnet
Currently garnet will not run due to double statistic registration of new
stats in ClockedObject. This occurs because a temporary array named 'cls'
is being added as a child to garnet internal and external link SimObjects.
This patch simply renames the temporary array which prevents it from
being added as a child object and avoids the assertion that a statistic
was already registered.

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 10:31:37 -05:00
Matthias Jung
86e9a6ffec ext: Update DRAMPower
Sync DRAMPower to external tool

This patch syncs the DRAMPower library of gem5 to the external
one on github (https://github.com/ravenrd/DRAMPower) of which
I am a maintainer.

The version used is the commit:
902a00a1797c48a9df97ec88868f20e847680ae6
from 07.  May.  2016.

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 10:31:36 -05:00
Matthias Jung
137e244bda misc: SystemC Elastic Trace Player Example.
This patch adds an example configuration for elastic trace playing into the
SystemC world, similar to the already existing traffic generator example in
/util/tlm.

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 10:31:33 -05:00
Christian Menard
b8064c8209 misc: fix a compile error due to incompability with SystemC 2.3.1
This patch fixes an ambigous call compile error

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 09:50:18 -05:00
Abdul Mutaal Ahmad
9c20880fb5 mem: tester for new HMC configuration
This patch provides the example test script to configure different HMC
architecture and run traffic through traffic generator.

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 09:48:43 -05:00
Abdul Mutaal Ahmad
7cb0c7bd65 mem: different HMC configuration
In this new hmc configuration we have used the existing components in gem5
mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different
architecture for HMC.

Highlights

1- It explores 3 different HMC architectures

2- It creates 4-HMC crossbars and attaches 16 vault controllers with it.
This  will connect vaults to serial links

3- From the previous version, HMCController with round robin funtionality
is being removed and all the serial links are being accessible directly
from user ports

4- Latency incorporated by HMCController (in previous version) is being
added to SerialLink

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 09:45:21 -05:00
Andreas Sandberg
57e3f40100 style: Fix incorrect references style verifiers
The style checker for spacing around control statements (ControlSpace)
and the whitespace checker (Whitespace) didn't refer to some of their
configuration variables correctly. This changeset fixes those issues.

Reported-by: Jason Lowe-Power <power.jg@gmail.com>

--HG--
extra : amend_source : 05d82d27d4c42aacd78b514d3ca35ca5744164bb
2016-07-01 15:35:52 +01:00
Abdul Mutaal Ahmad
1051223318 misc: Separate stats file for SystemC-gem5 co-simulation
In previous versions of systemC-gem5 coupling statistics were not updated
for the systemc-gem5 simulation. systemC-gem5 simulation only need the
previously built config.ini file and normal gem5 simulation has to be run
once to generate config.ini file. Thus stats.txt inside the m5out folder is
redundant for systemC-gem5 simulation. A new stats file is now generated
with the all the statistics for systemC-gem5 simulation. This will also
resolve the stats issue in tlm-sysmtemC simulation.

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 09:30:15 -05:00
Andreas Hansson
50e9d0df51 scons: Track swig packages when loading embedded swig code
This patch changes how the embedded swig code is loaded to ensure that
gem5 works with swig 3.0.9. For Python 2.7 and above, swig 3.0.9 now
relies on importlib, and actually looks in the appropriate packages,
even for the wrapped C code. However, the swig wrapper does not
explicitly place the module in the right package (it just calls
Py_InitModule), and we have to take explicit action to ensure that the
swig code can be loaded. This patch adds the information to the
generated wrappers and the appropriate calls to set the context as
part of the swig initialisation.

Previous versions of swig used to fall back on looking in the global
namespace for the wrappers (and still do for Python 2.6), but
technically things should not work without the functionality in this
patch.
2016-06-28 03:50:00 -04:00
Andreas Sandberg
9c8710430e stats: Update stats to reflect ARM changes 2016-06-21 16:42:04 +01:00
Nikos Nikoleris
1fac3a292a arm: Mark uninitialized new TLB entries as not valid
Previously when we initialized the TLB we would allocate a number of
TLB entries which would be marked as valid. As a result the TLB
contained an entry which would be considered a valid entry for the 0
page.

Change-Id: I23ace86426a171a4f6200ebeb29ad57c21647036
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-20 15:51:31 +01:00
Reiley Jeapaul
0e80ee7778 sim: Added library include to fix build errors on clang-703.0.31
The use of array tuples, requires an explicit include of the array library

Change-Id: I06730051777a97edf80e41a5604184b387b12239
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-20 15:34:41 +01:00
Nikos Nikoleris
40e4453ddc mem: Fix the snoop filter when there is a downstream addr mapper
The snoop filter handles requests in two steps which preceed and
follow the call to send the packet downstream. An address mapper could
possibly change the address of the packet when it is sent downstream
breaking the snoop filter assumption that the address is unchanged

Change-Id: Ib2db755e9ebef4f2f7c0169a46b1b11185ffbe79
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-20 15:11:18 +01:00
Andreas Sandberg
dd0f54fed6 tests: Add a test command to get test status as an exit code
Add a "test" command to tests.py that queries a test pickle file and
returns different exit codes depending on the outcome of the tests in
the file. The following exit codes can currently be returned:

  * 0: All tests were successful or skipped.

  * 1: General fault in the script such as incorrect parameters or
    failing to parse a pickle file.

  * 2: At least one test failed to run. This is what the summary
    formatter usually shows as a 'FAILED'.

  * 3: All tests ran correctly, but at least one failed to verify
    its output. When displaying test output using the summary
    formatter, such a test would show up as 'CHANGED'.

The command can be invoked like this:

./tests/tests.py test `find build/ARM/tests/opt/ -name status.pickle`

Change-Id: I7e6bc661516f38ff08dfda7c4359a1e10bf97864
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-06-20 14:50:43 +01:00
Andreas Sandberg
96b74fd31b tests: Split test results into running and verification
The test base class already assumes that test cases consists of a run
stage and a verification stage. Reflect this in the results class to
make it possible to detect cases where a run was successful, but
didn't verify.

Change-Id: I31ef393e496671221c5408aca41649cd8dda74ca
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-06-20 14:50:34 +01:00
Gabor Dozsa
ddfc4c4593 style: catch trailing white spaces in make and dts files
Change-Id: I2a4f1893919660e51599902b972a6f3f5717e305
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-20 14:49:52 +01:00
Andreas Sandberg
efb7fb6f85 mem: Resolve TrafficGen trace relative to the config
The traffic generator currently resolves relative trace paths relative
to gem5's current working directory. This can lead to surprising
results for relative paths where the expectation would normally be
that they are resolved relative to the configuration file. This
changeset implements config-relative trace file lookups. The old
behavior is kept as a fallback for configs that expect that behavior.

Change-Id: I1bda4e16725842666ffc37dcb6838c23a6ff138c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-06-20 14:49:37 +01:00
Andreas Hansson
2c91ccfbe8 config: Fix omission of walker cache in config scripts
This patch ensures a walker cache is instantiated if specfied.

Change-Id: I2c6b4bf3454d56bb19558c73b406e1875acbd986
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
2016-06-20 14:39:49 +01:00
Andreas Sandberg
37bb0d0fb3 kern, arm: Dump dmesg on kernel panic/oops
Add helper functions to dump the guest kernel's dmesg buffer to a text
file in m5out. This functionality is split into two parts. First, a
dmesg dump function that can be used in other places:

void Linux::dumpDmesg(ThreadContext *, std::ostream &)

This function is used to implement two PCEvents: DmesgDumpEvent and
KernelPanic event. The only difference between the two is that the
latter produces a gem5 panic instead of a warning in addition to
dumping the kernel log.

Change-Id: I6d2af1d666ace57124089648ea906f6c787ac63c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-06-20 14:39:49 +01:00
Andreas Sandberg
60fb5e79f3 base: Fix multiple names to one address bug in SymbolTable
The SymbolTable class currently assumes that at most one symbol can
point to a given address. If multiple symbols point to the same
address, only the first one gets added to the internal symbol table
since there is already a match in the address table.

This changeset converts the address table from a map into a multimap
to be able to handle cases where an address maps to multiple
symbols. Additionally, the insert method is changed to not fail if
there is a match in the address table.

Change-Id: I6b4f1d5560c21e49a4af33220efb2a8302961768
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-06-20 14:39:48 +01:00
Tuan Ta
bb9033c26b gpu-compute: Fixed a bug in decoding Atomic ST
There is a mismatch between DataType and SrcDataType in constructing
Atomic ST instruction. The mismatch causes atomic_store and
atomic_store_explicit function to store incorrect value in memory.
2016-06-18 13:02:13 -04:00
Steve Reinhardt
54aeb1a187 stats: update EIO stats 2016-06-12 20:02:49 -04:00
jkalamat
3724fb15fa gpu-compute: parametrize Wavefront size
Eliminate the VSZ constant that defined the Wavefront size (in numbers of work
items); replaced it with a parameter in the GPU.py configuration script.
Changed all data structures dependent on the Wavefront size to be dynamically
sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at
initialization time.
2016-06-09 11:24:55 -04:00
Mohammad Alian
e5b7b6780f dist, dev: Fixed the packet ordering in etherswitch
This patch fixes the order that packets gets pushed into the output fifo
of etherswitch. If two packets arrive at the same tick to the etherswitch,
we sort and push them based on their source port id.
In dist-gem5 simulations, if there is no ordering inforced while two
packets arrive at the same tick, it can lead to non-deterministic simulations

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-06-08 09:12:41 -05:00
Andreas Hansson
8d177d128f sim: Make clang happy
Once again appeasing clang.
2016-06-07 14:27:49 +01:00
Sergei Trofimov
0257fdee91 sim: added missing include to mathexpr.hh
mathexpr.hh uses std::function<> but was not including the appropriate
header, which resulted in an error

build/ARM/sim/mathexpr.hh:51:18: error: 'function' in namespace 'std'
does not name a template type
     typedef std::function<double(std::string)> EvalCallback;

This commit adds the missing include.

Change-Id: I6c01d77d4354c6de838538f137a38f75f9866166
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-06-07 14:27:35 +01:00
Andreas Sandberg
85997e66a0 stats: Add power stats to test references
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 17:16:44 +01:00