Commit graph

8103 commits

Author SHA1 Message Date
Gabe Black 72d35701e9 X86: Mark prefetches as such in their instruction and request flags. 2011-03-01 22:42:18 -08:00
Nilay Vaish 3a10b200f7 Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF()
has not been provided with correct number of arguments. The patch fixes these
bugs.
2011-03-01 15:26:11 -06:00
Gabe Black 9e608a6ad7 SCons: Separately label the global non-sticky options.
The global sticky options were being printed with a heading, and then the
global nonsticky options were being printed immediately after them without a
heading. Because the two lists ran together and the first had its own heading,
it looked like -all- those options where sticky even though some of them
aren't. This change adds a label to the second list so it's clear they're
different.
2011-03-01 03:00:42 -08:00
Gabe Black 993e83ef80 Ruby: Mention that Ruby's bound checking option only applies to Ruby. 2011-03-01 02:59:09 -08:00
Gabe Black d3214c5c5e X86: If PCI config space is disabled, pass through to regular IO addresses. 2011-02-27 16:25:06 -08:00
Gabe Black b84ae9bd40 X86: Update X86_FS stats. 2011-02-27 16:24:54 -08:00
Gabe Black 0ce5d31159 X86: Use regular read requests in the walker instead of read exclusive. 2011-02-27 16:24:10 -08:00
Korey Sewell 8135b81ae4 inorder: bzip2 regression update 2011-02-27 14:17:26 -05:00
Nathan Binkert 586564895f getopt: Remove GPL code.
This code is unused and should never have been committed
2011-02-26 21:43:11 -08:00
Nilay Vaish a4c038764d Ruby: Remove store buffer
This patch removes the store buffer from Ruby. It is not in use currently.
Since libruby is being and store buffer makes calls to libruby, it is not
possible to maintain it until substantial changes are made.
2011-02-25 17:55:20 -06:00
Nilay Vaish e7edd270aa Ruby: Remove libruby
This patch removes libruby_internal.hh, libruby.hh and libruby.cc. It moves
the contents to libruby.hh to RubyRequest.hh and RubyRequest.cc files.
2011-02-25 17:54:56 -06:00
Nilay Vaish 6bf7153104 Ruby: Make Address.hh independent of RubySystem
This patch changes Address.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depend on
RubySystem have been moved to Address.cc file.
2011-02-25 17:51:56 -06:00
Nilay Vaish 80b3886475 Ruby: Make DataBlock.hh independent of RubySystem
This patch changes DataBlock.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depende on
RubySystem have been moved to DataBlock.cc file.
2011-02-25 17:51:02 -06:00
Timothy M. Jones a10685ad1e O3CPU: Fix iqCount and lsqCount SMT fetch policies.
Fixes two of the SMT fetch policies in O3CPU that were returning the count
of instructions in the IQ or LSQ rather than the thread ID to fetch from.
2011-02-25 13:50:29 +00:00
Gabe Black aa0cd52504 Configs: Explicitly import env in Benchmarks.py
env was being implicitly imported into Benchmarks.py through SysPaths.py.
This change brings it in explicitly in the file where it's used.
2011-02-24 02:14:45 -08:00
Brad Beckmann ae52ff631f regress: MOESI_hammer memtest updates 2011-02-23 16:41:59 -08:00
Brad Beckmann 12a05c23b7 ruby: automate permission setting
This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code.  No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.

--HG--
rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py
rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
2011-02-23 16:41:59 -08:00
Brad Beckmann 7842e95519 MOESI_hammer: cache probe address clean up 2011-02-23 16:41:58 -08:00
Brad Beckmann 3bc33eeaea ruby: cleaned up access permission enum 2011-02-23 16:41:58 -08:00
Brad Beckmann c09a33e5d5 ruby: removed unsupported protocol files 2011-02-23 16:41:26 -08:00
Korey Sewell 72fb282ab1 inorder: add 00.gzip and 60.bzip2 regression tests 2011-02-23 16:35:25 -05:00
Korey Sewell 0a74246fb9 inorder: InstSeqNum bug
Because int and not InstSeqNum was used in a couple of places, you can
overflow the int type and thus get wierd bugs when the sequence number
is negative (or some wierd value)
2011-02-23 16:35:18 -05:00
Korey Sewell 3e1ad73d08 inorder: dyn inst initialization
remove constructors that werent being used (it just gets confusing)
use initialization list for all the variables instead of relying on initVars()
function
2011-02-23 16:35:04 -05:00
Korey Sewell e0a021005d inorder: cache packet handling
-use a pointer to CacheReqPacket instead of PacketPtr so correct destructors
get called on packet deletion
- make sure to delete the packet if the cache blocks the sendTiming request
or for some reason we dont use the packet
- dont overwrite memory requests since in the worst case an instruction will
be replaying a request so no need to keep allocating a new request
- we dont use retryPkt so delete it
- fetch code was split out already, so just assert that this is a memory
reference inst. and that the staticInst is available
2011-02-23 16:30:45 -05:00
Ali Saidi 73603c2b17 ARM: Update regression tests for preceeding changes. 2011-02-23 15:10:50 -06:00
Ali Saidi 057598843a Mem: Print out memory when access > 8 bytes 2011-02-23 15:10:50 -06:00
Ali Saidi 2eb19dac65 ARM: Set ITSTATE correctly after FlushPipe 2011-02-23 15:10:50 -06:00
Ali Saidi 916c7f162d ARM: This panic can be hit during misspeculation so it can't exist. 2011-02-23 15:10:50 -06:00
Ali Saidi 1201c5a134 ARM: Bad interworking warn way to noisy when running real code w/misspeculation. 2011-02-23 15:10:50 -06:00
Ali Saidi f9d4d9df1b O3: When a prefetch causes a fault, don't record it in the inst 2011-02-23 15:10:50 -06:00
Giacomo Gabrielli 7ee2de31c4 ARM: NEON instruction templates modified to set the predicate flag to false when needed. 2011-02-23 15:10:50 -06:00
Ali Saidi 3de8e0a0d4 O3: If there is an outstanding table walk don't let the inst queue sleep.
If there is an outstanding table walk and no other activity in the CPU
it can go to sleep and never wake up. This change makes the instruction
queue always active if the CPU is waiting for a store to translate.

If Gabe changes the way this code works then the below should be removed
as indicated by the todo.
2011-02-23 15:10:49 -06:00
Ali Saidi 326191adc9 ARM: Squash state on FPSCR stride or len write. 2011-02-23 15:10:49 -06:00
Matt Horsnell bb319a589e ARM: Mark store conditionals as such. 2011-02-23 15:10:49 -06:00
Ali Saidi 7391ea6de6 ARM: Do something for ISB, DSB, DMB 2011-02-23 15:10:49 -06:00
Ali Saidi ae3d456855 ARM: Fix bug that let two table walks occur in parallel. 2011-02-23 15:10:49 -06:00
Ali Saidi f05f35df99 Includes: Don't include isa_traits.hh and use the TheISA namespace unless really needed. 2011-02-23 15:10:49 -06:00
Ali Saidi 805ad4ba41 ARM: Make Noop actually decode to a noop and set it's instflags. 2011-02-23 15:10:49 -06:00
Ali Saidi 68bd80794c O3: Fix bug when a squash occurs right before TLB miss returns.
In this case we need to throw away the TLB miss, not assume it was the
one we were waiting for.
2011-02-23 15:10:49 -06:00
Ali Saidi e572cf93ee ARM: Delete OABI syscall handling.
We only support EABI binaries, so there is no reason to support OABI syscalls.
The loader detects OABI calls and fatal() so there is no reason to even check
here.
2011-02-23 15:10:48 -06:00
Ali Saidi 511c637ab0 CLCD: Fix some serialization bugs with the clcd controller. 2011-02-23 15:10:48 -06:00
Ali Saidi 79dac89552 ARM: Clarifies creation of Linux and baremetal ARM systems.
makeArmSystem creates both bare-metal and Linux systems more cleanly.
machine_type was never optional though listed as an optional argument; a system
such as "RealView_PBX" must now be explicitly specified.  Now that it is a
required argument, the placement of the arguments has changed slightly
requiring some changes to calls that create ARM systems.
2011-02-23 15:10:48 -06:00
Ali Saidi e2a6275c03 ARM: Add support for read of 100MHz clock in system controller. 2011-02-23 15:10:48 -06:00
Ali Saidi 2157b9976b ARM: Reset simulation statistics when pref counters are reset.
The ARM performance counters are not currently supported by the model.
This patch interprets a 'reset performance counters' command to mean 'reset
the simulator statistics' instead.
2011-02-23 15:10:48 -06:00
Ali Saidi d63020717c ARM: Adds dummy support for a L2 latency miscreg. 2011-02-23 15:10:48 -06:00
Korey Sewell 981e1dd7ee configs: cache: add cache line size option 2011-02-23 14:26:55 -05:00
Korey Sewell fb92578415 configs: set default cache params
It's confusing (especially to new users), when you are setting some standard
parameters (as defined in Options.py) and they aren't reflected in the simulations
so we might as well link the settings in CacheConfig.py to those in Options.py
2011-02-23 01:01:46 -05:00
Korey Sewell 78c37b8048 ruby: extend dprintfs for RubyGenerated TraceFlag
"executing" isnt a very descriptive debug message and in going through the
output you get multiple messages that say "executing" but nothing to help
you parse through the code/execution.

So instead, at least print out the name of the action that is taking
place in these functions.
2011-02-23 00:58:42 -05:00
Korey Sewell 67cc52a605 ruby: cleaning up RubyQueue and RubyNetwork dprintfs
Overall, continue to progress Ruby debug messages to more of the normal M5
debug message style
- add a name() to the Ruby Throttle & PerfectSwitch objects so that the debug output
isn't littered w/"global:" everywhere.
- clean up messages that print over multiple lines when possible
- clean up duplicate prints in the message buffer
2011-02-23 00:58:40 -05:00
Brad Beckmann 63a25a56cc m5: merged in hammer fix 2011-02-22 11:16:40 -08:00