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Author SHA1 Message Date
Gabe Black
65fedeb5a7 Made x86 ExtMachInsts distinguishable from each other by defining a real == and a real hash function. 
--HG--
extra : convert_revision : 30f29a36f6ab44e67e62aaf81b685fbe1267c746
 2007-04-04 14:27:00 +00:00
Gabe Black
6010c6ded4 Added all the different variations of the register names. 
--HG--
extra : convert_revision : ff06bdca556a5e1a0dfe7978575c2277c30c002a
 2007-04-04 14:25:36 +00:00
Kevin Lim
9e1f3bc11a Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head

--HG--
extra : convert_revision : 4a8cbb65b19636c31b5c6fd5f24c90f8f2148ed1
 2007-04-04 00:14:44 -04:00
Gabe Black
10fe8b05db Made the "data" field of store queue entries into a character array. It's sized to match an IntReg which was what it used to be, but we might want to make it something architecture independent. All data is now endian converted before entering the store queue entries which simplifies store to load forwarding in "trans endian" simulations, and makes twin memory ops work. 
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
    fixed twin memory operations.

--HG--
extra : convert_revision : 8fb97f98e285cd22413e06e146fa82392ac2a590
 2007-04-03 22:53:26 +00:00
Ali Saidi
30f101881f Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem 
into  zizzer.eecs.umich.edu:/tmp/newmem.1449b

--HG--
extra : convert_revision : 05021f4884de7af769df9f9c4416c483baa9c2fe
 2007-04-03 18:29:09 -04:00
Ali Saidi
4c555cffa9 fixed sttw instruction changes execution trace a bit 
--HG--
extra : convert_revision : 4bebe6f9acedfd29dfe02f16d4ddb551a2fc7290
 2007-04-03 18:28:59 -04:00
Kevin Lim
98c8cd0b36 Fix a memory leak. Hopefully this fixes the longer running benchmarks. 
--HG--
extra : convert_revision : 89eff82642ff181a9b95c77c4d2bf620ca837113
 2007-04-03 14:25:24 -04:00
Gabe Black
93d4c624c5 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 7be8ebe55a7b11552d78701520f93aa86db1e501
 2007-04-03 15:01:36 +00:00
Gabe Black
61c56ffeaf A batch of changes and fixes. Macroops are now generated automatically, multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented. 
--HG--
extra : convert_revision : 518059f47e11df50aa450d4a322ef2ac069c99c9
 2007-04-03 15:01:09 +00:00
Gabe Black
0ce6936e7d Zero out ModRM if the byte isn't there, and fix some displacement size stuff. 
--HG--
extra : convert_revision : f43abf33a223a665b30098c63011fb162200d5e6
 2007-04-03 14:56:24 +00:00
Kevin Lim
ec09e5ad6f Remove/comment out DPRINTFs that were causing a segfault. 
The removed ones were unnecessary.  The commented out ones could be useful in the future, should this problem get fixed.  See flyspray task #243.

src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
    Remove/comment out DPRINTFs that were causing a segfault.

--HG--
extra : convert_revision : b5aeda1c6300dfde5e0a3e9b8c4c5f6fa00b9862
 2007-04-02 13:55:45 -04:00
Kevin Lim
24cc5227af Fix up SPARC's CPU builder to match changes to Alpha's CPU builder. 
--HG--
extra : convert_revision : ec2a739f1da07f0922c772e6998017995115ce80
 2007-04-02 13:28:17 -04:00
Kevin Lim
5c97b56eb5 Update refs for recent changes. 
--HG--
extra : convert_revision : 30a02eec4d83c4e1708ed0a4e2b5faea88fe8e03
 2007-03-30 16:59:40 -04:00
Ali Saidi
c46e946c94 Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 2f7f50f4ad31f741c0c67db96e49d30ca078fc94
 2007-03-29 22:01:34 -04:00
Ali Saidi
528694817f make serialization at least seem to work 
--HG--
extra : convert_revision : cbfdb64f9a204670b8dd0294c74a17044b9f330c
 2007-03-29 22:00:01 -04:00
Gabe Black
ac191ecc78 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : e6a6c65cb0f8df9af82daa3eebd989c4211edfb0
 2007-03-29 22:43:38 +00:00
Gabe Black
1d3253abfe Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem 
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-mcf

--HG--
extra : convert_revision : f2c3503e8893b957330cf3791748a45800ea5a82
 2007-03-29 17:43:37 -05:00
Gabe Black
db6ed0eee2 Added SPARC_SE simple timing twolf regression. 
--HG--
extra : convert_revision : 289aadd4bc762a5a9e7a82ee15196ebdea2521e5
 2007-03-29 17:41:20 -05:00
Gabe Black
85c1e89444 Added a SPARC_SE simple timing mcf regression. 
--HG--
extra : convert_revision : d8fea11c37bd3f0b5f5e8880c92b711892ee8125
 2007-03-29 17:39:34 -05:00
Ali Saidi
8ca218cab5 get rid of CWP bounds warning... 
--HG--
extra : convert_revision : 74df09341c091c2d6ca9b46c6a3521f22b48acf4
 2007-03-29 15:57:11 -04:00
Ali Saidi
370b712360 add to instruction test sttw instruction 
--HG--
extra : convert_revision : 16efbe12e609a909a589505ad6c473eb44c38f9c
 2007-03-29 15:41:09 -04:00
Gabe Black
7fcc9d2106 Made the MultiOp format do a little more. It now sets up single microop instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support. 
--HG--
extra : convert_revision : 1a0a4b36afce8255e23e3cdd7a85c1392dda5f72
 2007-03-29 17:57:19 +00:00
Gabe Black
e67a207ad3 Add a microcode assembler. A microcode "program" is a series of statements. Each statement has an optional label at the beginning, a capitilized microcode class name which is roughly equivalent to a mnemonic in a regular ISA, and then an optional series of operands seperated by white space. The operands are either a decimal constant, a label, or a code fragment surrounded by non nested {}s. Labels are a letter or underscore followed by letters, underscores, or digits. The syntax for describing code segments might need to be changed if a need arrises to have {}s in the code itself. 
--HG--
extra : convert_revision : 8e5cfdd1a3c9a7e3731fdf6acd615ee82ac2b9b7
 2007-03-29 17:57:18 +00:00
Gabe Black
5c4cc4b552 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem 
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-vortex

--HG--
extra : convert_revision : 709766f1a1a2347c92d4f508e38b9602c1030717
 2007-03-29 12:57:17 -05:00
Gabe Black
0f2201c1fe Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem 
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-vortex

--HG--
extra : convert_revision : 7efa5fe80ef75155685b93453e967a1115318b9d
 2007-03-29 12:53:36 -05:00
Gabe Black
484214db78 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem 
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-gzip

--HG--
extra : convert_revision : 39cf24fe19cd48306baef1ef147a3f4738d0fe8a
 2007-03-29 12:52:09 -05:00
Gabe Black
d3b0ea3eeb Added SPARC_SE simple timing vortex regression. 
--HG--
extra : convert_revision : 12a2fc0b43cfa72747c1ef24d124979e43b166c7
 2007-03-29 12:51:12 -05:00
Gabe Black
7fd748d7fc Added SPARC_SE simple timing gzip regression. 
--HG--
extra : convert_revision : 3d5f5f991c9b0c1c07499a2013119240cae5870f
 2007-03-29 12:49:59 -05:00
Kevin Lim
5c3f724174 Override addPrivateSplitL1Caches function in order to automatically set the tgts_per_mshr of the caches to 20. This is needed otherwise things will potentially lock up when using the O3CPU because the caches can run out of targets, and then not respond. 
Remove this hack once the caches eventually get fixed.

--HG--
extra : convert_revision : 8c61ac1b6182f57ebbe3bcfeddb5a4f4334d7bc0
 2007-03-29 12:25:47 -04:00
Kevin Lim
80af6530f6 Update code so that the O3 CPU can handle not initially having anything hooked up to its ports. This fixes the segfault Ali recently found when using sampling. 
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
    Update code so that the O3 CPU can handle not initially having anything hooked up to its ports.

--HG--
extra : convert_revision : 04bcef44e754735d821509ebd69b0ef9c8ef8e2c
 2007-03-29 12:02:57 -04:00
Gabe Black
14a7cda195 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  ewok.(none):/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 849b63ae1300e240082da19dfeb283cdeeb80aef
 2007-03-29 00:51:34 -07:00
Gabe Black
77ce05f478 Fidget with the syntax of the MultiOp format in anticipation of making it actually work. 
--HG--
extra : convert_revision : f62a1f035cc11677df8eb5a839ca1247d819fab3
 2007-03-29 00:50:54 -07:00
Gabe Black
fd77212b72 Add code to generate register and immediate based integer op microop classes. 
--HG--
extra : convert_revision : 718f941da74dd3b4557cd21e1772879ac21aa9c6
 2007-03-29 00:49:53 -07:00
Gabe Black
0d5f6167ff Allow "let" blocks to add code to the output files. 
--HG--
extra : convert_revision : 0ffddb2b40dccbf2a3790464c843cfc1b43eaa02
 2007-03-29 00:47:46 -07:00
Ron Dreslinski
8a674bed5c Call compare and Swap on the target, not the response. 
--HG--
extra : convert_revision : 522805fe2c9abaa5ba0d9262ad98f841d90f6452
 2007-03-28 14:38:11 -05:00
Ali Saidi
e95bc9d8f9 some more fixes... non-tso stuff seems to work 
--HG--
extra : convert_revision : da604d20443376d04826397d0aaff0bdd744053b
 2007-03-27 20:44:21 -04:00
Ron Dreslinski
55614caecc Merge zizzer:/bk/newmem 
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head

--HG--
extra : convert_revision : 45b64b1564f0e4958d8441455f87b2b185324d55
 2007-03-27 17:06:07 -05:00
Ron Dreslinski
6b8cd9d06d First Pass At Cmp/Swap in caches 
--HG--
extra : convert_revision : 211bfb7c6a59e9e120dae1600d4754baaf231332
 2007-03-27 17:05:25 -05:00
Nathan Binkert
d8ca2d3b16 Instead of creating a new python process to run traceflags.py, 
just directly exec the file and generate the flags

--HG--
extra : convert_revision : d648ca7348404ded5337db327adafccbd2ae40c8
 2007-03-26 21:07:32 -07:00
Ali Saidi
01ac962a06 Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 4b60e96e8dc9c69842514e29925ec1931597ddb4
 2007-03-26 18:40:30 -04:00
Ali Saidi
e8dc1723ee first bit of life from the intel gigabit model 
--HG--
extra : convert_revision : d8944a53f6b585df21651c4e624518d5c49a7837
 2007-03-26 18:40:18 -04:00
Kevin Lim
4e0ec56868 Update stats for changes. 
--HG--
extra : convert_revision : a24c4cd7e2fcd732f5da5679f0c0fbf205f22815
 2007-03-25 01:05:48 -04:00
Kevin Lim
5c044cf1f6 Update for new trace data behavior. 
--HG--
extra : convert_revision : c3df20c5187614febc4cc9f4d4c68bfecfba1ea7
 2007-03-24 23:47:14 -05:00
Kevin Lim
4bad33ce9d Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2

--HG--
extra : convert_revision : f3d193dd1e0b82c496d8224f014123b7cb028c02
 2007-03-24 14:00:16 -04:00
Gabe Black
5e61e07613 Added a SPARC_SE simple atomic regression for the mcf benchmark. 
--HG--
extra : convert_revision : 2284e41c03659db8fc8f284f7d9b587a3708fadf
 2007-03-24 02:14:24 -05:00
Gabe Black
e7bbd85ae6 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : 6b1c8025d29f3e8f90906805dd51a5d523d56004
 2007-03-23 21:47:03 -04:00
Kevin Lim
047f77102b Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2

src/cpu/base_dyn_inst.hh:
    Hand merge.  Line is no longer needed because it's handled in the ISA.

--HG--
extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
 2007-03-23 13:20:19 -04:00
Kevin Lim
2330adfa28 Make hardware loads/stores serializing; they need to avoid certain out-of-order interactions in the 21264. 
--HG--
extra : convert_revision : d83940af7d0e8efe891d574ac42c6d70d179e2b1
 2007-03-23 13:14:05 -04:00
Kevin Lim
941d3168d0 Updates for commit. 
1. Move interrupt handling to a separate function to clean up main commit() function a bit.  Also gate the function call off properly based on whether or not there are outstanding interrupts, and the system is not in PAL mode.
2. Better handling of updating instruction's status bits.  Instructions are not marked "atCommit" until other stages view it (pushed off to IEW/IQ), and they have been properly handled (faults).
3. Don't consider the ROB "empty" for the purpose of other stages until the ROB is empty, all stores have written back, and there was no store commits this cycle.  The last is necessary in case a store committed, in which case it would look like all stores have written back but in actuality have not.

src/cpu/o3/commit.hh:
    Slightly modify how interrupts are handled.  Also include some extra bools to keep track of state properly.
src/cpu/o3/commit_impl.hh:
    Slightly modify how interrupts are handled.  Also include some extra bools to keep track of state.

    General correctness updates, most specifically for when commit broadcasts to other stages that the ROB is empty.

--HG--
extra : convert_revision : 682ec6ccf4ee6ed0c8a030ceaba1c90a3619d102
 2007-03-23 13:13:10 -04:00
Kevin Lim
78de00091b 3 memory system fixes: 
1. Update packet's flags properly when a snoop happens
2. Don't allow accesses to read a block's data if the block has outstanding MSHRs.  This avoids a RAW hazard in MP systems that the memory system was not detecting properly earlier (a write required a block to upgrade, and while the upgrade was outstanding, a read came along and read old data).
3. Update MSHR's request upon a response being handled.  If the MSHR has more targets than it can respond to in one cycle, then its request must be properly updated to the new head of the targets list.

src/mem/bus.cc:
    Update packet's flags properly upon snoop.
src/mem/cache/cache_impl.hh:
    Be sure to not allow accesses to a block with outstanding MSHRs.
src/mem/cache/miss/miss_queue.cc:
    Update MSHR's request upon a response being handled.

--HG--
extra : convert_revision : 76a9abc610ca3f1904f075ad21637148a41982d6
 2007-03-23 13:09:37 -04:00