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Added SPARC_SE simple timing gzip regression.

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extra : convert_revision : 3d5f5f991c9b0c1c07499a2013119240cae5870f
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Gabe Black 2007-03-29 12:49:59 -05:00
parent 14a7cda195
commit 7fd748d7fc
5 changed files with 646 additions and 0 deletions
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187
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini Normal file
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[root]
type=Root
children=system
dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
clock=1
cpu_id=0
defer_registration=false
function_trace=false
function_trace_start=0
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
phase=0
progress_interval=0
system=system
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
clock=1000
responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
egid=100
env=
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
output=cout
pid=100
ppid=99
system=system
uid=100
[system.membus]
type=Bus
bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
zero=false
port=system.membus.port[0]

178
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out Normal file
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[root]
type=Root
dummy=0
[system.physmem]
type=PhysicalMemory
file=
range=[0,134217727]
latency=1
zero=false
[system]
type=System
physmem=system.physmem
mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
clock=1000
width=64
responder_set=false
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
input=cin
output=cout
env=
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
system=system
uid=100
euid=100
gid=100
egid=100
pid=100
ppid=99
[system.cpu]
type=TimingSimpleCPU
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
progress_interval=0
system=system
cpu_id=0
workload=system.cpu.workload
clock=1
phase=0
defer_registration=false
// width not specified
function_trace=false
function_trace_start=0
// simulate_stalls not specified
[system.cpu.toL2Bus]
type=Bus
bus_id=0
clock=1000
width=64
responder_set=false
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

230
tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt Normal file
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---------- Begin Simulation Statistics ----------
host_inst_rate 531377 # Simulator instruction rate (inst/s)
host_mem_usage 154376 # Number of bytes of host memory used
host_seconds 2803.12 # Real time elapsed on the host
host_tick_rate 1212716 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514860 # Number of instructions simulated
sim_seconds 0.003399 # Number of seconds simulated
sim_ticks 3399390003 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 2848.782706 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1848.782706 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 551182478 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 357702478 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 3103.285714 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2103.285714 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 21723 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 14723 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3023.717816 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2023.717816 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 785395584 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 525650584 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1255.221220 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 2949.038694 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency
system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1336578062 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses
system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 883353062 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 2949.038694 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 568905105 # number of overall hits
system.cpu.dcache.overall_miss_latency 1336578062 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses
system.cpu.dcache.overall_misses 453225 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 883353062 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 449136 # number of replacements
system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4068.114109 # Cycle average of tags in use
system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 33495000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 316447 # number of writebacks
system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3979.992714 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.992714 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 4370032 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 3272032 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1356569.911658 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3979.992714 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency
system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 4370032 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 3272032 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3979.992714 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1489513763 # number of overall hits
system.cpu.icache.overall_miss_latency 4370032 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 1098 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 3272032 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 115 # number of replacements
system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 865.251814 # Cycle average of tags in use
system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 3215.864263 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1941.261615 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 87423270 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 52773197 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 316438 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.000028 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 9 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.000028 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 9 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 27.352695 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 3215.864263 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 87423270 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 52773197 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 3214.799956 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 743583 # number of overall hits
system.cpu.l2cache.overall_miss_latency 87423270 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 27194 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 52773197 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 2632 # number of replacements
system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 23773.580402 # Cycle average of tags in use
system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 2531 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 3399390003 # number of cpu cycles simulated
system.cpu.num_insts 1489514860 # Number of instructions executed
system.cpu.num_refs 569359656 # Number of memory references
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
---------- End Simulation Statistics ----------

7
tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr Normal file
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@ -0,0 +1,7 @@
warn: More than two loadable segments in ELF object.
warn: Ignoring segment @ 0xb4000 length 0x10.
warn: More than two loadable segments in ELF object.
warn: Ignoring segment @ 0x0 length 0x0.
0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
warn: Ignoring request to flush register windows.

44
tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout Normal file
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spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
M5 Simulator System
Copyright (c) 2001-2006
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 29 2007 03:54:03
M5 started Thu Mar 29 03:54:23 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 3399390003 because target called exit()