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fixed sttw instruction changes execution trace a bit

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--HG--
extra : convert_revision : 4bebe6f9acedfd29dfe02f16d4ddb551a2fc7290
This commit is contained in:
Ali Saidi 2007-04-03 18:28:59 -04:00
parent 26c0426e44
commit 4c555cffa9
5 changed files with 10141 additions and 25 deletions
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6
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
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@ -1,11 +1,7 @@
[root]
type=Root
children=system
checkpoint=
clock=2000000000
max_tick=0
output_file=cout
progress_interval=0
dummy=0
[system]
type=SparcSystem

5
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out
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@ -1,9 +1,6 @@
[root]
type=Root
clock=2000000000
max_tick=0
progress_interval=0
output_file=cout
dummy=0
[system.physmem]
type=PhysicalMemory

20
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt
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@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1214495 # Simulator instruction rate (inst/s)
host_mem_usage 409828 # Number of bytes of host memory used
host_seconds 1828.73 # Real time elapsed on the host
host_tick_rate 1214601 # Simulator tick rate (ticks/s)
host_inst_rate 571923 # Simulator instruction rate (inst/s)
host_mem_usage 373992 # Number of bytes of host memory used
host_seconds 3905.40 # Real time elapsed on the host
host_tick_rate 571972 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 2220985165 # Number of instructions simulated
sim_seconds 1.110589 # Number of seconds simulated
sim_ticks 2221178828 # Number of ticks simulated
sim_insts 2233583679 # Number of instructions simulated
sim_seconds 1.116889 # Number of seconds simulated
sim_ticks 2233777512 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2221178829 # number of cpu cycles simulated
system.cpu.num_insts 2220985165 # Number of instructions executed
system.cpu.num_refs 545896474 # Number of memory references
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
system.cpu.num_insts 2233583679 # Number of instructions executed
system.cpu.num_refs 547951940 # Number of memory references
---------- End Simulation Statistics ----------

10126
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr
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File diff suppressed because it is too large Load diff

9
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout
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@ -5,8 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 3 2007 19:48:02
M5 started Sat Mar 3 19:58:15 2007
M5 executing on zeep
M5 compiled Mar 30 2007 12:26:45
M5 started Fri Mar 30 12:26:47 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
Exiting @ tick 2221178828 because m5_exit instruction encountered
Global frequency set at 2000000000 ticks per second
Exiting @ tick 2233777512 because m5_exit instruction encountered