Commit graph

2162 commits

Author SHA1 Message Date
Gabe Black
5705354616 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : d3e160f6e938af5d2118883f8d7c91fa29a0ccaa
2006-02-24 18:45:46 -05:00
Gabe Black
e66f521d5b Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

SConscript:
arch/alpha/ev5.cc:
dev/alpha_console.cc:
    Hand merged

--HG--
extra : convert_revision : 318a671e6803400d3ed086a90e70d6790e4f6b19
2006-02-24 18:45:28 -05:00
Gabe Black
e5f75c2549 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : c167d2bec89120258124bf34ada3adf23e3e8188
2006-02-24 18:33:57 -05:00
Lisa Hsu
4d01be373e Merge zizzer:/bk/m5
into  zed.eecs.umich.edu:/z/hsul/work/m5/clean

--HG--
extra : convert_revision : 34314698d4248a078c7b43125b2d048280ff576d
2006-02-24 18:08:55 -05:00
Lisa Hsu
fcb9718dcd 1) make it pretty for large clusters
2) make subticks vertical so they can be longer
3) make inner and outer axes farther apart to make room for subtick's vertical labels

--HG--
extra : convert_revision : 91a1aab3f1078921edd53428e6712744210c9f1b
2006-02-24 18:08:14 -05:00
Steve Reinhardt
7a37037358 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/stever/bk/multiarch

arch/isa_parser.py:
    SCCS merged

--HG--
extra : convert_revision : 080cca7616b37db3bf18976b63b3dbcb47d8b918
2006-02-24 08:52:38 -05:00
Gabe Black
802fd04f64 Removed a stray ::.
--HG--
extra : convert_revision : f6114b78e30e8cba5af6276042b0f043d8773739
2006-02-24 03:51:21 -05:00
Gabe Black
08637efadc Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type.
arch/alpha/alpha_memory.cc:
arch/alpha/isa/decoder.isa:
    Added news where faults are created.
arch/alpha/ev5.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==
arch/alpha/faults.cc:
arch/alpha/faults.hh:
    Changed Fault to be a RefCountingPtr
arch/alpha/isa/fp.isa:
    Added a new where a FloatEnableFault was created.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
    Added a new where an UnimplementedFault is created.
base/refcnt.hh:
    Added include of stddef.h for the NULL macro
cpu/base_dyn_inst.cc:
    Added a new where an UnimplementedOpcodeFault is created.
cpu/o3/alpha_cpu_impl.hh:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name()
cpu/o3/regfile.hh:
    Added new where UnimplementedOpcodeFaults are created.
cpu/simple/cpu.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created.
dev/alpha_console.cc:
    Added news where MachineCheckFaults are created.
dev/pcidev.hh:
    Added news where MachineCheckFaults are generated.
dev/sinic.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables.
kern/kernel_stats.cc:
    Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future.
kern/kernel_stats.hh:
    Commented out the declaration of _fault. when fault() is called, the fault increments its own stat.
sim/faults.cc:
sim/faults.hh:
    Changed Fault from a FaultBase * to a RefCountingPtr.

--HG--
extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d
2006-02-24 01:51:45 -05:00
Gabe Black
a5f8392d34 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 77dc4dda9c72c871364e112ae8b10669b8d8fc86
2006-02-23 19:32:38 -05:00
Korey Sewell
f6cac25dcf name changes ...
SConscript:
    change to alpha_memory.hh

--HG--
rename : arch/alpha/memory.cc => arch/alpha/alpha_memory.cc
rename : arch/alpha/memory.hh => arch/alpha/alpha_memory.hh
extra : convert_revision : 62b1a41de22701160f04cb7a78242746cfcde819
2006-02-23 18:46:12 -05:00
Steve Reinhardt
51647e7bec Enable building only selected CPU models via new scons
CPU_MODELS parameter.  For example:
scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug
Unfortunately the option is not sticky due to a scons
bug with saving & restoring ListOption parameters.

SConscript:
    Separate out cpu-model-specific files so they can be conditionally
    included based on value of new CPU_MODELS parameter.
    Most of these are now handled in cpu/SConscript, except for FullCPU
    which is still in this file.
arch/SConscript:
    The set of CPU-model-specific execute files must now be
    determined from the CPU_MODELS parameter, via the new
    cpu_models.py file.
    Also pass the list of configured CPU models to isa_parser.py.
arch/isa_parser.py:
    Move CpuModel definition and objects out to a
    separate file so they can be shared with scons.
    Global list of CPU models to generate code for is now
    controlled by command-line parameters (so we can do
    only a subset of the available ones).
build/SConstruct:
    Define new CPU_MODELS ListOption.
cpu/static_inst.hh:
    Rename static_inst_impl.hh to static_inst_exec_sigs.hh.

--HG--
extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 17:00:29 -05:00
Ali Saidi
4f831bc561 ev5.cc:
SCCS merged

arch/alpha/ev5.cc:
    SCCS merged

--HG--
extra : convert_revision : 9d70c1d461dab0ec016fd0616d74a49942aac659
2006-02-23 15:08:08 -05:00
Ali Saidi
e1c3acd91c Merge zizzer:/bk/m5
into  zeep.eecs.umich.edu:/z/saidi/work/m5.head

cpu/simple/cpu.cc:
    remove initCPU from constructor
dev/alpha_console.cc:
    we are panicing, so no need to return a fault

--HG--
extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9
2006-02-23 15:06:06 -05:00
Ali Saidi
1166d4f0bf Get rid of the xc from the alphaAccess/alphaConsole backdoor device.
Now allocate an array of stacks indexed by cpu number which specify
cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for
their stacks before continuing. This change *REQUIRES* a the new
console code to operate correctly.

arch/alpha/ev5.cc:
    Add cpuId to initCPU/initIPR functions
cpu/o3/cpu.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Move the cpu initilization into an init() function since it now needs
    the CPU id which isn't known at construction
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
    instead of the bootstrap variables, add space for 64 cpu stacks in the
    alpha access structure.
sim/system.cc:
    start all cpus immediately rather than just the first one

--HG--
extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b
2006-02-23 14:50:16 -05:00
Steve Reinhardt
99484cfae8 Create a Builder object for .isa files in arch/SConscript.
Start using SCons File objects to avoid fixed paths in
subordinate SConscripts.

SConscript:
    Push isa_parser stuff (including .isa scanner) down into
    arch/SConscript.
arch/SConscript:
    Create a Builder object for .isa files, including existing scanner.
    Return file objects generated by isa-specific SConscript
    back up to parent.
arch/alpha/SConscript:
arch/mips/SConscript:
arch/sparc/SConscript:
    Convert sources to scons File objects, so file names can be specified
    relative to the current directory.
    Invoke new builder for isa description, and get generated sources from
    there (instead of listing them explicitly).
arch/isa_parser.py:
    Get rid of third argument ("include_path").
    It was a pain to generate this from scons, and it turned out
    it's not needed anyway, since the only included file
    (decoder.hh) will be in the same directory as the sources.

--HG--
extra : convert_revision : 36861bcef36763f229704d8cb7a642b4486a3581
2006-02-23 14:31:15 -05:00
Kevin Lim
9949ccf161 Cast enum to int to fix compile error from regression.
--HG--
extra : convert_revision : 2d998ec7393e1c08c7552f7e586160d579eab2b1
2006-02-23 13:27:23 -05:00
Steve Reinhardt
cdb5fd9d12 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/stever/bk/m5

--HG--
extra : convert_revision : 38367d6d1fa594b84b64e5930588904719a40c08
2006-02-23 08:17:09 -05:00
Steve Reinhardt
c13ea339dc Add pipe() syscall to Alpha Linux emulation.
arch/alpha/alpha_linux_process.cc:
    Add pipeFunc.

--HG--
extra : convert_revision : c094d2dff993d5e60bc43b7cd4b9586c15c634a3
2006-02-23 08:16:59 -05:00
Gabe Black
8ed320792c Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : d92c611475aef2b911f76e2c21be12096e73048a
2006-02-23 04:11:09 -05:00
Gabe Black
5ecaaa0fb0 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : 850077a56aead260aa4bbd3df60b672a931d57ed
2006-02-23 04:08:55 -05:00
Nathan Binkert
f462266b30 don't add an empty suboption description
--HG--
extra : convert_revision : 594744c3d438aed08a23db376959930071b2c368
2006-02-23 00:21:35 -05:00
Nathan Binkert
35094fb0fe make it possible to add filters for job names so that
parts of the full crossproduct of jobs can be ignored.

--HG--
extra : convert_revision : c44b3daea0cf4b487b1d99eae92da16573b15930
2006-02-23 00:20:32 -05:00
Nathan Binkert
cc60bc49e6 fix stat name
--HG--
extra : convert_revision : 4c0f8c1b6ba1e77dc302b8ece3c8822b9b4a05ee
2006-02-23 00:00:01 -05:00
Steve Reinhardt
f67a99d1c9 Auto-generate arch/foo.hh "switch headers" in scons.
SConscript:
    Include new arch/SConscript file.
arch/isa_specific.hh:
    Get rid of unnecessary ISA_INCLUDE() macro and other
    things that were used only for that purpose.
build/SConstruct:
    Move list of ISAs to env var ALL_ISA_LIST.

--HG--
extra : convert_revision : 612c7ee4279d57209662be88dc577d80fdbd692c
2006-02-22 22:22:06 -05:00
Steve Reinhardt
9a4c0f12ef Clean excess comments out of SConscripts.
SConscript:
arch/alpha/SConscript:
    Clean out excess comments.

--HG--
extra : convert_revision : 7aae68d36f9fce5f236d117d803b5e3cd4a3769d
2006-02-22 21:11:45 -05:00
Gabe Black
b37f5da98f Cleaned up the mapping of isa_parser.py inputs to outputs.
--HG--
extra : convert_revision : a8431a67001b2916eb8d0548f1f34e1c948bb356
2006-02-22 20:52:03 -05:00
Korey Sewell
9bc7f13eeb make sure alpha still compiles , rename files back to original naming ...
Now that we have decoder.do, add new files so we can start compiling other files
needed for MIPS syscall emulation mode

arch/mips/linux_process.cc:
arch/mips/linux_process.hh:
    New MIPS-specific file

--HG--
rename : arch/alpha/linux_process.cc => arch/alpha/alpha_linux_process.cc
rename : arch/alpha/linux_process.hh => arch/alpha/alpha_linux_process.hh
rename : arch/alpha/tru64_process.cc => arch/alpha/alpha_tru64_process.cc
rename : arch/alpha/tru64_process.hh => arch/alpha/alpha_tru64_process.hh
extra : convert_revision : 2bfc27e8772523cbeb95f40684f9a32fe5554f87
2006-02-22 04:08:08 -05:00
Korey Sewell
2d2510e94f Still builds "../MIPS_SE/arch/mips/decoder.do with no errors!
-----
uncomment out detailed model ... just commented to supress some compile errors

arch/isa_parser.py:
    uncomment out detailed model ... just commented to supress some compile errors

--HG--
extra : convert_revision : e884b9bd47794409f74043ad1aca6dadd1323185
2006-02-22 03:44:21 -05:00
Korey Sewell
54b47bc5ae MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!!
arch/mips/faults.hh:
    remove nonsense
arch/mips/isa/base.isa:
    define R31
arch/mips/isa/bitfields.isa:
    forgotten bitfields
arch/mips/isa/decoder.isa:
    INT64 -> int64_t
arch/mips/isa/formats.isa:
    fix comments
arch/mips/isa/formats/branch.isa:
    Branch -> BranchLikely
    RB -> RT
arch/mips/isa/formats/fp.isa:
    Make FP ops generates
arch/mips/isa/formats/mem.isa:
    RA,RB -> RS,RT
arch/mips/isa/formats/noop.isa:
    Rc -> Rd
arch/mips/isa/formats/util.isa:
    forgot brace and semicolon
arch/mips/isa/includes.isa:
    remove unnecessary files
arch/mips/isa_traits.hh:
    spacing
cpu/static_inst.hh:
    add cond_delay_slot flag

--HG--
extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
2006-02-22 03:33:35 -05:00
Korey Sewell
37cd6695eb Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/multiarch

--HG--
rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh
extra : convert_revision : c641ba3c1009829b7276279b2dca441be1da5b30
2006-02-21 22:06:18 -05:00
Korey Sewell
a4799a89de Renaming alpha files and changing some MIPS stuff to be more like Alpha version
SConscript:
    changed the alpha_memory.hh to memory.hh in SConscript
arch/isa_parser.py:
    temporarily comment out o3 model
arch/mips/isa/base.isa:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
    Fix Up Base Class to mirror how Alpha generates StaticInsts
arch/mips/faults.cc:
    MIPS fault.cc file
arch/mips/faults.hh:
    MIPS fault.hh file

--HG--
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh
rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh
extra : convert_revision : f92d6e765ca96a8b952aef79ed119fa29464563b
2006-02-21 22:02:05 -05:00
Gabe Black
8d80fd1477 Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
2006-02-21 20:10:40 -05:00
Gabe Black
3f7979c99d Made Addr a global type
--HG--
extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835
2006-02-21 03:38:21 -05:00
Gabe Black
74d7cd1cea Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : da72b3593037c2a67a56c799e292853b8aece907
2006-02-20 23:55:25 -05:00
Gabe Black
466284b5d2 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 9d386beecc6d13625ff19ca72cbc3628dcd59d3c
2006-02-20 23:54:38 -05:00
Gabe Black
c226648459 Finished the implementing the change of the ISA from a class to a namespace
dev/sinic.cc:
    When DPRINTF disappears, reg32 becomes an unused variable. With -Werror, this causes the compile to fail.

--HG--
extra : convert_revision : c003c714228491e060155070d192521c53d9e929
2006-02-20 23:53:14 -05:00
Nathan Binkert
3a0102536b Get rid of the code that delays PIO write accesses
until the cache access occurs.  The fundamental problem
is that a subsequent read that occurs functionally will
get a functionally incorrect result that can break
driver code.

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
    get rid of pio_delay write and the associated code to move
    the write to the cache access function
dev/sinicreg.hh:
    no more write delays
python/m5/objects/Ethernet.py:
    get rid of pio_delay write

--HG--
extra : convert_revision : 1dcb51b8f4514e717bc334a782dfdf06d29ae69d
2006-02-20 23:41:50 -05:00
Korey Sewell
bdf3fd92ba make MIPS specific
--HG--
extra : convert_revision : c019fad60fbf1a316bc6201b8ce8acf5a9875989
2006-02-20 14:48:10 -05:00
Korey Sewell
19534176e0 load/store instruction format ... now generates load/store code
and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.

arch/mips/isa/bitfields.isa:
    comment change
arch/mips/isa/decoder.isa:
    re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
    Define LoadMemory & Store Memory formats
    Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
    Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
    change shw->sh and uhw->uh

--HG--
extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
2006-02-20 14:30:23 -05:00
Korey Sewell
38ce95db3b Support for All Jump Instructions ...
Redo format for Branches and Jumps ( Must update NNPC not NPC )

Now all branches and jumps look like they auto-generate correctly from isa_parser.py!!!

arch/mips/isa/decoder.isa:
    Support for All Jump Instructions ..
arch/mips/isa/formats/branch.isa:
    Redo format for Branches and Jumps ( Must update NNPC not NPC )
arch/mips/isa/formats/util.isa:
    define clear_exe_inst_hazards for later use

--HG--
extra : convert_revision : 63618ed12ee6ed94c47d29619cc1cab2cbaf5cda
2006-02-20 01:49:16 -05:00
Gabe Black
7c642b7106 Reapplied changes which were undone by a pull
arch/alpha/faults.hh:
kern/linux/linux.hh:
    Added typedef for Addr
kern/tru64/tru64.hh:
    Fixed up namespaces

--HG--
extra : convert_revision : bf968e615bc0acc96abeb0eec0872f5b02b5a065
2006-02-19 04:00:05 -05:00
Gabe Black
f721a4d9ad Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

arch/alpha/faults.hh:
    ur
    Using cleaned up fault class deiffinitions

--HG--
extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
2006-02-19 03:20:05 -05:00
Gabe Black
ed25d32617 Remade some changes which were undone
cpu/base.hh:
cpu/static_inst.hh:
    Changed include of targetarch/isa_traits.hh back to arch/isa_traits.hh
cpu/exec_context.hh:
    Changed Fault back to Fault *

--HG--
extra : convert_revision : 410f2e2472f8aa5bf92619a5defdf85f689a5597
2006-02-19 03:04:44 -05:00
Gabe Black
0e4a80df1a Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 090b30a7f70294e1aeb13ba0bc15da4061bdf348
2006-02-19 02:34:52 -05:00
Gabe Black
463aa6d49d Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
    Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
    Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
    Added using directive for AlphaISA
arch/alpha/ev5.hh:
    Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
    Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
    Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
    Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
    Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
    Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
    Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
    Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
    Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
    Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
    Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
    Added a typedef for Addr
base/loader/symtab.hh:
    Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
    Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
    Added typedefs for Addr and MachInst
cpu/base.cc:
    Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
    Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
    Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
    Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
    Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
    Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
    Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
    Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
    Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
    Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
    Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
    untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
    Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
    Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
    Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
    Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
    Cleaned up namespace issues
cpu/o3/cpu.hh:
    Cleaned up namespace usage
cpu/o3/decode.hh:
    Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
    Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
    Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
    Removed typedef of ISA
cpu/o3/iew_impl.hh:
    Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
    Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
    Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
    Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
    Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
    Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
    Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
    Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
    Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
    Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
    Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
    Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
    Untemplatized StaticInst
cpu/static_inst.hh:
    Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
    Added using namespace AlphaISA
dev/simple_disk.hh:
    Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
    Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
    Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
    Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
    Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
    Added TheISA to Addr type in structs
sim/process.hh:
    Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
    Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
    Added typecast for Addr, and TheISA namespace specifier for where needed

--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
2006-02-19 02:34:37 -05:00
Ali Saidi
14f2cdb1a1 Merge zizzer:/bk/m5
into  pb15.local:/Users/ali/work/m5.head

--HG--
extra : convert_revision : 774e4afbb0f9c3ae62843138b6d7195ea184ff92
2006-02-19 00:47:45 -05:00
Ali Saidi
00d58aeb4d forgot a negative sign
--HG--
extra : convert_revision : 9cdb00198979fca831d3e6840f9c534671ccead3
2006-02-19 00:28:53 -05:00
Ali Saidi
53d2c9398e Move Linux/Tru64 architecture independent code into kern/*
leaving dependent code making way  for solaris linux syscall emu.

SConscript:
    Add two new files for syscall emulation
    Add getDesc() function
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    move architecture independent code into kern/linux/linux.(hh|cc)
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.hh:
    Add getDesc function
kern/linux/linux.hh:
    move generi linux syscall emulation code into kern/linux
kern/tru64/tru64.hh:
    move generi tru64 syscall emulation code into kern/tru64
sim/process.cc:
sim/process.hh:
    Push the function determination and calling stuff down to LiveProcess
    and out of the Linux/Tru64 classes respectively
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    fnctl implementation was identical in tru64 and linux so moved to generic

--HG--
extra : convert_revision : 103293dbe6fe2f7892de4929d17dc085def77026
2006-02-18 23:44:22 -05:00
Korey Sewell
a48c24b61e Support NNPC and branch instructions ... Outputs to decoder.cc correctly
Edits to the CPU model may still need to be made to handle branch likely insts...

arch/isa_parser.py:
    add a NNPC operand ...
arch/mips/isa/base.isa:
    change SPARC to MIPS
arch/mips/isa/decoder.isa:
    typo < to >=
arch/mips/isa/formats/basic.isa:
    spacing
arch/mips/isa/formats/branch.isa:
    add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
    support for NNPC and R31
arch/mips/isa_traits.hh:
    NNPC Addr variable

--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
2006-02-18 23:17:45 -05:00
Gabe Black
bf4fb61fa1 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 8b2759d670a6a60142be748817ccef736d61dabf
2006-02-18 20:58:26 -05:00