SConscript:
Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
Replaced htoa() with gtoh().
dev/disk_image.cc:
Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
Got rid of magic numbers.
Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
Got rid of unnecessary macros.
Changed RegType_t to IdeRegType.
Changed bmi_regs to allow accessing registers by name instead of just by array index.
Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
Made ReadConfig and WriteConfig begin with a lower-case letter.
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
Added classes for RTC and PIT modules.
dev/tsunamireg.h:
Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
Got rid of a magic number.
Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
Replaced htoa() with htog().
python/m5/objects/Pci.py:
PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
TsunamiFake was renamed as IsaFake.
sim/system.cc:
Replaced htoa()s with htog()s.
dev/isa_fake.cc:
New BitKeeper file ``dev/isa_fake.cc''
TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
New BitKeeper file ``dev/isa_fake.hh''
TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
New BitKeeper file ``dev/pitreg.h''
Useful macros for working with PIT (Periodic Interval Timer) registers.
--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
dev/pciconfigall.cc:
removed union.
dev/pcidev.cc:
.
dev/rtcreg.h:
more macros to avoid magic numbers.
dev/tsunami_io.cc:
replaced magic numbers, no more advancing RTC as it isn't reaaly necessary.
dev/tsunami_io.hh:
removed declarations of things that go unused.
dev/uart8250.cc:
reading the Interrupt ID register should clear TX interrupt flag.
dev/uart8250.hh:
useful #defines.
kern/freebsd/freebsd_system.cc:
kern/freebsd/freebsd_system.hh:
nothing.
python/m5/objects/Pci.py:
new PciFake.
--HG--
extra : convert_revision : 88259704f5b215591d1416360180810fcda14d26
SConscript:
Include pcifake.cc, fix spacing.
dev/ide_ctrl.cc:
Consolidate switch-case blocks.
dev/ide_disk.cc:
Add comments.
dev/pciconfigall.cc:
Adjust spacing.
dev/pcidev.cc:
Adjust spacing, rearrange code.
dev/tsunami_io.cc:
Rearrange code.
dev/uart8250.cc:
Switch uart interrupt interval back to original value.
python/m5/objects/Pci.py:
Add PciFake class to be used as a PCI-ISA bridge device.
--HG--
extra : convert_revision : 8aea94318510079a310377f297aa161ba5f7864c
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/pcidev.cc:
Made endian-independent.
dev/ide_disk.hh:
fixed.
dev/pciconfigall.cc:
The data to write is contained in a 32-bit unsigned int now. The union method would not have worked on big-endian machines.
dev/pcidev.hh:
Fixed typo.
dev/tsunami_io.cc:
Return zero on RTC alarm reads.
dev/uart8250.cc:
Fix uart interrupt handling.
--HG--
extra : convert_revision : b5c08e8e77644c399c20888666406805ff1b6649
dev/ide_disk.cc:
Fix formatting. Panic if unexpected register type is given.
python/m5/objects/Tsunami.py:
Add default size of TsunamiFake device.
--HG--
extra : convert_revision : 03a35a2f6468b95746cba41ce7e93afeeb70ccef
dev/ide_atareg.h:
Need endian.h for LITTLE_ENDIAN.
sim/syscall_emul.hh:
Need to include sys/fcntl.h to get O_BINARY.
--HG--
extra : convert_revision : 606f9506dc483f3952dcc65b8ba25c28001f2c43
Make the AlphaConsole calculate the number of CPUs instead
of passing that in as a parameter.
cpu/base.cc:
pass the desired cpu_id into registerExecContext, offsetting it
by the thread number. a cpu_id of -1 means that it should be
generated for you.
cpu/base.hh:
Take the cpu_id as a parameter
cpu/o3/alpha_cpu_builder.cc:
cpu/simple/cpu.cc:
Accept the cpu_id as a parameter
while we're here, let's remove the multiplier since it is
not used.
dev/alpha_console.cc:
don't take the number of CPUs as a parameter. Calculate it from
the system based on the number of CPUs that have been registered.
move init() code to startup() to ensure that all CPUs are registerd.
dev/alpha_console.hh:
python/m5/objects/AlphaConsole.py:
don't take the number of CPUs as a parameter.
move init() code to startup() to ensure that all CPUs are registerd.
python/m5/objects/BaseCPU.py:
take the cpu_id as a parameter. Default it to -1 which means
that it will be generated.
sim/system.cc:
allow the registerExecContext functioin to take a desired
cpu_id as a parameter. Check to ensure that the id isn't
already used. Accept -1 as a request to have an id assigned.
sim/system.hh:
keep track of the number of registered exec contexts.
provide a function for accessing the number of exec contexts
that checks to ensure that they are all registered correctly.
--HG--
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code into a function that can be called by the AlphaConsole class.
AlphaConsole will pass in its address.
arch/alpha/ev5.hh:
Move Phys2K0Seg to ev5.hh and fixup the TSUNAMI uncacheable
bits so that they will be converted correctly.
dev/alpha_access.h:
Do not hard code the location of the AlphaConsole
dev/alpha_console.cc:
fixup #includes
tell the system where the alpha console is
sim/system.hh:
Provide a function that will tell the system where the AlphaAccess
structure (device) lives
--HG--
extra : convert_revision : 92d70ca926151a32eebe9925de597459ac58013e
instead of compiling it into the console version
dev/alpha_access.h:
move serialization stuff to alpha_console.hh
define the ALPHA_ACCESS_BASE in m5 instead of in console.c and
have m5 pass the value to the console
dev/alpha_console.cc:
dev/alpha_console.hh:
Move serialization stuff into a derived class of AlphaAccess
sim/system.cc:
pass the value of ALPHA_ACCESS_BASE to the console code via
the m5AlphaAccess console variable.
--HG--
extra : convert_revision : 0ea4ba239f03d6dad51a6efae0385aa543064117
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/ide_disk.hh:
Add support for 32-bit accesses.
dev/ns_gige.cc:
Change default configuration register value to work with FreeBSD driver.
--HG--
extra : convert_revision : c9dd125338a97ffa8cd95293e6b7877068652387
dev/alpha_access.h:
Update the ALPHA_ACCESS_VERSION
move typedefs to this file since they're only used here.
dev/alpha_console.cc:
formatting
sim/system.cc:
xxm -> m5
--HG--
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the nsgige state machine can run. The frequency is of the actual
state transitions, and not the rate of what underlying
instructions might run at.
dev/ns_gige.cc:
Implement a state machine clock that acutally limits how fast
the state machine can run. After each state transition, a
variable is kept to hold the next state transition until the
next clock. The frequency is of the actual state transitions,
and not the rate of what underlying instructions might run at.
dev/ns_gige.hh:
Add back the rxKickEvent and txKickEvent events.
python/m5/objects/Ethernet.py:
Default the state machine clock to '0ns' so the default
behaviour doesn't change when we actually implement the
state machine clock.
--HG--
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dev/ide_disk.cc:
Make ide disk set interrupts correctly.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Implement read of timer counts.
kern/freebsd/freebsd_system.cc:
kern/freebsd/freebsd_system.hh:
Remove SkipFuncEvents that we don't need to skip.
python/m5/objects/Tsunami.py:
Add size parameter to TsunamiFake class.
--HG--
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clean up debugging a bit
dev/ns_gige.cc:
little bit of formatting
don't break in the debugger if a packet is dropped when the
receiver is disabled since it can realistically happen
--HG--
extra : convert_revision : 364efa3eb16990db191085f5b847c3bb255a173c
SConscript:
Added kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
Added Argument to support replacement of calibrate_clocks function in FreeBSD.
dev/ns_gige.hh:
Fixed NIC model number typo.
dev/tsunami_io.cc:
Added support for RTC writes and PIC 2 mask reads. Made RTC static member.
dev/tsunami_io.hh:
Made RTC static member.
kern/freebsd/freebsd_system.cc:
Added events to skip functions in FreeBSD.
kern/freebsd/freebsd_system.hh:
Added events to skip certain functions.
--HG--
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dev/pcidev.cc:
Allow writes to some PCI read-only registers.
Fix problem when writing to a zero offset IO location.
dev/tsunami_io.cc:
Fix calculation of IO addresses.
Add registers for keyboard and PCI DMA.
dev/tsunamireg.h:
Add registers for keyboard and PCI DMA.
python/m5/objects/System.py:
Allow generic System to be instantiated.
--HG--
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Doxyfile:
Turn on EXTRACT_ALL so we get full class hierarchy info.
base/range.hh:
cpu/o3/fetch.hh:
cpu/o3/rename_map.hh:
cpu/o3/rob.hh:
dev/ide_disk.cc:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.hh:
Fix doxygen issues.
--HG--
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kern/linux/sched.hh:
kern/linux/thread_info.hh:
got rid of everything but exactly what we needed
util/categories.py:
newest version from one of my repositories
--HG--
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Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
Minor tweaks on Frequency/Latency:
- added new Clock param type to avoid ambiguities
- factored out init code into getLatency()
- made RootFrequency *not* a subclass of Frequency so it
can't be directly assigned to a Frequency paremeter
--HG--
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clean up code to eliminate license issues.
dev/ns_gige.cc:
dev/ns_gige_reg.h:
clean up code to eliminate license issues.
--HG--
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can pass simulator specific options to the device driver.
dev/ns_gige.cc:
Add the m5 register and parameter to the ns83820 device model
so that we can pass simulator specific options to the device
driver.
dev/ns_gige.hh:
dev/ns_gige_reg.h:
Add the m5 register to the ns83820 device model
--HG--
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CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
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