Commit graph

2368 commits

Author SHA1 Message Date
Ron Dreslinski
7f114ca419 Many changes that make the new mem system compile. Now to convert the rest of the tree to use the new mem system.
mem/mem_object.hh:
    Create constrtor so it compiles
mem/packet.hh:
    Fix typedefs so they compile, add in a few more headers for compilation
mem/page_table.cc:
    convert to new mem system so it compiles
mem/page_table.hh:
    fix it to the version that had asid support.  Make it compile in the new system
mem/physical.cc:
    Fix some compilation bugs
mem/physical.hh:
    Add a type that made compile fail
mem/port.hh:
    Fix a spelling error that messed up compilation
mem/request.hh:
    fix typedefs and forward declerations so it compiles

--HG--
extra : convert_revision : 580fb1ba31ada799ff0122601b8b5a8d994bb8af
2006-02-15 14:21:09 -05:00
Korey Sewell
a0cdf213ab ...
arch/mips/isa/base.isa:
    restore base.isa

--HG--
extra : convert_revision : a551caae28f505b22bceae3297fc00b0fb6a0e23
2006-02-15 14:08:54 -05:00
Kevin Lim
2d04f18674 Gives separate methods for initiating and completing a memory access, which will be helpful for the merged memory model.
arch/alpha/isa/mem.isa:
    Include methods that allow a memory operation to be split between the part that initiates the access, and the part that completes the access.  In these functions the Mem variable is explicitly declared; in the default execute functions, the Mem variable is still handled through %(op_decl)s.
arch/isa_parser.py:
    Include recording the type of the memory access variable so that it can be used if it needs to be explicitly declared in a template.

    Have memory operands consider themselves neither a source nor a destination to avoid including themselves on the op_src_decl list or the op_dest_decl list.

    Record op_src_decl and op_dest_decl lists to allow for declaring only source or destination operands.  This is needed for the split memory access methods.

--HG--
extra : convert_revision : f674f7a2f747ae40ba8c3a0933b0337c87ee0b6c
2006-02-15 13:05:21 -05:00
Ali Saidi
7b42d61f13 Merge zizzer:/bk/m5
into  pb15.local:/Users/ali/work/m5.head

sim/byteswap.hh:
    SCCS merged

--HG--
extra : convert_revision : 65989fef265ddfafb59a6c96e3cdde76eb3e071d
2006-02-15 01:27:06 -05:00
Ali Saidi
18a0fa3e0c endian fixes and compiles on mac os x
arch/alpha/alpha_linux_process.cc:
    add endian conversions for fstat functions
arch/alpha/alpha_tru64_process.cc:
    add endian conversions for various functions
sim/byteswap.hh:
    for some reason gcc on macos really wants long and unsigned long
    Why int32_t and uint32_t isn't sufficient I don't know.
sim/process.cc:
sim/syscall_emul.hh:
    endian fixes

--HG--
extra : convert_revision : ce625d5660b70867c43c74fbed856149c0d8cd36
2006-02-15 01:23:13 -05:00
Korey Sewell
aee1bf5873 Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 5b0a3dd1a52ca9b29ea4a1c505a7435bfd6110fe
2006-02-14 22:43:26 -05:00
Korey Sewell
23bbec6a34 another big step to a parsable ISA ... no errors after I used a symbolic link for
arch/alpha/main.isa to test my files ...

arch/mips/isa/operands.isa:
    use sd and ud instead of sdw and udw

--HG--
extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
2006-02-14 22:43:14 -05:00
Korey Sewell
5830200d78 trying to get ISA to parse correctly ...
arch/mips/isa/formats/unimp.isa:
    holds unimplemented formats
arch/mips/isa/formats/unknown.isa:
    holds unknown formats

--HG--
extra : convert_revision : 0f3a8ea7e3a1592322cce54527d6989152e57975
2006-02-14 21:26:01 -05:00
Gabe Black
7826fcd09d New files to fix building the SPARC_SE and MIPS_SE isa_parser.py generated files.
--HG--
extra : convert_revision : 94a9543376f8b4709a4aef54c5ac0d6f582a9dad
2006-02-14 20:13:08 -05:00
Gabe Black
085b73fe44 Fixed a path in the alpha isa description.
--HG--
extra : convert_revision : 2a73ef7703ffe5c5232619698a16c8b4ee265a21
2006-02-14 03:57:42 -05:00
Korey Sewell
9f584bcc6f Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 62d9346c44d5b7d455414fbebf0da3a8ef8d0754
2006-02-14 02:12:39 -05:00
Korey Sewell
d7ac2b56c2 make MIPS MT instructions decodable ...
arch/mips/isa/bitfields.isa:
    extra bitfield for decoding

--HG--
extra : convert_revision : 27f0afc3ee6ce00a94f44b2b1ac160ec26030866
2006-02-14 02:03:14 -05:00
Gabe Black
19e5efed03 Pseudo instructions are now passed whatever instructions they need by the decoder, rather than extracting them explicitly. This lets most of the pseudo instruction code to be shared across architectures.
SConscript:
    Moved pseudo_inst.hh from targetarch to full system sources
arch/alpha/SConscript:
    Moved pseudo_inst.cc out of the alpha specific sources
arch/alpha/isa/decoder.isa:
    The decoder now pulls out the arguments for the pseudo instructions based on the alpha ABI
arch/alpha/isa/main.isa:
    Registers 16, 17 and 18 are used to get parameters for the pseudo instructions and can be referred to explicitly
sim/pseudo_inst.cc:
    Changed some include paths to reflect that pseudo_inst.hh is now outside of the alpha directory. Also, instead of extracting their parameters directly, they're passed in as regular function arguments.
sim/pseudo_inst.hh:
    Changed the function prototypes to include the functions parameters, now that they aren't extracted from the execution context.

--HG--
rename : arch/alpha/pseudo_inst.cc => sim/pseudo_inst.cc
rename : arch/alpha/pseudo_inst.hh => sim/pseudo_inst.hh
extra : convert_revision : 76ce768cf1d8a838aa7b64878a7ab4c4215ac999
2006-02-12 17:38:10 -05:00
Gabe Black
2c5e03550a Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh.
SConscript:
    Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh
    targetarch/isa_traits.hh is now included through arch/isa_traits.hh
    vptr.hh was removed from targetarch, and moved to sim
arch/alpha/pseudo_inst.cc:
    Moved vptr.hh from targetarch to sim
base/loader/object_file.hh:
base/loader/symtab.hh:
cpu/base.hh:
dev/ide_disk.cc:
    Changed the include of isa_traits.hh from targetarch to arch
cpu/static_inst.hh:
dev/platform.hh:
dev/simple_disk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/mbuf.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/process.hh:
sim/syscall_emul.hh:
    Changed the include of isa_traits.hh from targetarch to arch.
kern/linux/linux_threadinfo.hh:
    Changed the include of vptr.hh from targetarch to sim.
sim/byteswap.hh:
    Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t)
sim/vptr.hh:
    Fixed the assert in the equals operator.
    Changed the AlphaISA namespace reference to TheISA.
    Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures.
    Added an include of arch/isa_traits.hh so that TheISA would be defined.

--HG--
extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
2006-02-12 12:40:58 -05:00
Gabe Black
4d4c105ac5 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : baf9b0eb84df7da8152ddf9a25264e041a24b8ca
2006-02-12 12:17:51 -05:00
Gabe Black
47a065d9f0 vptr.hh:
Rename: arch/alpha/vptr.hh -> sim/vptr.hh

--HG--
rename : arch/alpha/vptr.hh => sim/vptr.hh
extra : convert_revision : 345745efec49f6169d1d9f61fd590240a995373b
2006-02-12 12:14:14 -05:00
Gabe Black
94590a4dba Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : 427b5c957f91e66271444acebc01e1a861790363
2006-02-12 11:38:26 -05:00
Steve Reinhardt
79613686f0 Polishing of isa_parser.py internal operand handling, resulting in
minor change to syntax of 'def operands' in ISA descriptions.

arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
    Change 'def operands' statement to work with new
    isa_parser changes.
arch/isa_parser.py:
    Merge OperandTraits and OperandDescriptor objects into a
    unified hierarchy of Operand objects.
    Required a change in the syntax of the 'def operands'
    statement in the ISA description.

--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
2006-02-12 00:31:19 -05:00
Steve Reinhardt
8f2e096275 Minor cleanup of operand type and traits code in isa_parser.py.
arch/isa_parser.py:
    Minor cleanup of operand type and traits code:
    - build operand size map right away when types are defined
    instead of waiting to do it lazily
    - check that operand types have been defined before operands
    - don't use 'type' as a variable name
    - use isinstance() instead of checking for types directly

--HG--
extra : convert_revision : 099c1ee8d490f9c38316749bf87209388c55c971
2006-02-11 21:26:49 -05:00
Steve Reinhardt
3cc6c59582 Add keyword parameters and list-valued arguments to
instruction format functions in ISA description language.

Take advantage of these features to clean up memory
instruction definitions in Alpha.

arch/alpha/isa/decoder.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
    Take advantage of new keyword parameters to disambiguate
    instruction vs. memory-request flags, and to provide
    a default EA calculation for memory ops (since 99% of them
    are the same).
arch/isa_parser.py:
    Add two new features to instruction format functions:
    - Keyword parameters, a la Python.
    - List-valued arguments.

    Also export makeList() function to Python code blocks,
    as this is handy for dealing with flags.

--HG--
extra : convert_revision : 99bbbaa2e765230aa96b6a06ed193793325f9fb0
2006-02-11 15:11:00 -05:00
Ali Saidi
59ba3d463c fix #if. I wonder why my compiler had no issues. Even though it is clearly
wrong

arch/alpha/alpha_linux_process.cc:
    fix #if. I wonder why my compiler had no issues

--HG--
extra : convert_revision : 880a0442b28811db5ec548ce940060d4b26ec634
2006-02-11 11:01:51 -05:00
Ali Saidi
96d6ac441c hello world works on a BE host for a LE guest
arch/alpha/alpha_linux_process.cc:
    Add endian conversions to fstat
sim/byteswap.hh:
    for some reason I don't understand g++ really wanted a long version defined
    even though int32_t should be the same.

--HG--
extra : convert_revision : 5bfe9d3f0b31824fa5a7ae3f51fd0be5ed4d555d
2006-02-11 00:55:36 -05:00
Ali Saidi
f2e97427be Merge zizzer:/bk/m5
into  pb15.local:/Users/ali/work/m5.head

--HG--
extra : convert_revision : b8631bcea38e3a75e4442927500ddfc7763ba9cf
2006-02-10 20:06:44 -05:00
Gabe Black
b070018266 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : 219377d0e4b70c30c17644991f39282b4aef14f8
2006-02-10 17:35:26 -05:00
Ali Saidi
ac6240896e confused an ifdef with an if
--HG--
extra : convert_revision : 5b8e8bdff5813cf8846e66de2652246d77c97e88
2006-02-10 14:59:37 -05:00
Ali Saidi
a86a3fa525 Merge zizzer:/bk/m5
into  udhcp-macvpn-776.public.engin.umich.edu:/Users/ali/work/m5.head

--HG--
extra : convert_revision : e9ffaa1d4b7eee1f5bd0c492e162aac1e0806099
2006-02-10 14:38:15 -05:00
Ali Saidi
fb7899aa68 fix problems on darwin/*BSD for syscall emulation mode
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    fixup for bsd hosts. Some headers are included by default which means that
    more variables need TGT_ prefixes and there isn't a stat call (everything
    is a stat64 call) so we have to work around that a bit
base/intmath.hh:
base/socket.cc:
    this is no longer needed with mac os 10.4
cpu/inst_seq.hh:
    just use a uint64_t instead of long long
cpu/o3/inst_queue_impl.hh:
    I much cleaner way to get max int
sim/syscall_emul.hh:
    fix stat64 problems on *BSD

--HG--
extra : convert_revision : 9eef5f896e083ae1774e818a9765dd83e0305942
2006-02-10 14:21:32 -05:00
Steve Reinhardt
3923eec0ef Change how memory operands are handled in ISA descriptions.
Should enable implementation of split-phase timing loads
with new memory model.
May create slight timing differences under FullCPU, as I
believe we were not handling software prefetches correctly
before when the split MemAcc/Exec model was used.  I haven't
looked into this in any detail though.

arch/alpha/isa/decoder.isa:
    HwLoadStore format split into separate HwLoad and
    HwStore formats.
    Copy instructions now fall under MiscPrefetch format.
    Mem_write_result is now just write_result in store
    conditionals.
arch/alpha/isa/mem.isa:
    Split MemAccExecute and LoadStoreExecute templates
    into separate templates for loads and stores; now
    that memory operands are handled differently from
    registers, it's impossible to have a single template
    serve both.
    Also unified the handling of "regular" prefetches
    (loads to r31) and "misc" prefetches (e.g., wh64)
    under the new scheme.  It looks like SW prefetches
    were not handled correctly in FullCPU up til now,
    since we generated an execute() method for the outer
    instruction but didn't generate a proper method for
    MemAcc::execute() (instead getting a default no-op
    method for that).
arch/alpha/isa/pal.isa:
    Split HwLoadStore into separate HwLoad and HwStore
    formats to select proper template (see change to
    mem.isa in this changeset).
arch/isa_parser.py:
    Stop trying to treat memory operands like register
    operands, since we never used them in a uniform way
    anyway, and it made it impossible to do split-phase
    loads as needed for the new CPU model.  Now there's no
    more 'op_mem_rd', 'op_nonmem_rd', etc.: 'op_rd' just does
    register operands, and the template code is responsible
    for formulating the call to the memory system.  Right now
    the only thing exported by InstObjParams is a new attribute
    'mem_acc_size' which gives the memory access size in bits,
    though more attributes can be added if needed.

    Also moved code in findOperands() method to
    OperandDescriptorList.__init__(), which is where it belongs.

--HG--
extra : convert_revision : 6d53d07e0c5e828455834ded4395fa40f9146a34
2006-02-10 09:12:55 -05:00
Korey Sewell
2865768112 Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : c78773ba1acb2c6a45f0e92d80fdfc7f23ea6973
2006-02-10 03:31:13 -05:00
Korey Sewell
5cfc5e8080 The first fully coded version of decoder.isa!!!!!
=================================================
-every MIPS32 ISA is represented with some type
of code block.
-any instruction that doesnt have a code block
would be of format WarnUnimpl. Examples of the
ones I am waiting on further info to implement
are the TLB register insts, memory consistency
instructions (ll,sc,etc.) and software debug
insts.

--HG--
extra : convert_revision : 4a26c72e4fa1f63b8689fe2631a7508daf660969
2006-02-10 03:27:19 -05:00
Steve Reinhardt
dd473ecd57 Split Alpha ISA description into multiple files
(thanks to Gabe's include feature!).

arch/alpha/isa/main.isa:
    Split out into multiple .isa files.

--HG--
extra : convert_revision : 30d8edf74ea194d4a208febf1e66edc72a7dbd5d
2006-02-09 23:02:38 -05:00
Steve Reinhardt
fb90b1dd13 Minor cleanup of include-handling code in isa_parser.py.
arch/isa_parser.py:
    Clean up ##include code a bit.
arch/sparc/isa/formats.isa:
arch/sparc/isa/main.isa:
    Fix include paths.

--HG--
extra : convert_revision : 0689963c2948e5f1088ecbf2cf6018d29bdaceff
2006-02-09 22:27:41 -05:00
Steve Reinhardt
2c528d5865 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/stever/bk/m5

--HG--
extra : convert_revision : 6e30fb802265c6a0d4afc00141b89ee529595549
2006-02-09 14:58:56 -05:00
Steve Reinhardt
730ee42ab8 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/stever/bk/m5

--HG--
extra : convert_revision : 10146c85d2fa6f565568cc30a4564b3674e4768d
2006-02-09 14:51:56 -05:00
Steve Reinhardt
879aaa5569 Change how isa_parser.py generates C++ names for isa_desc operands.
arch/isa_parser.py:
    Get rid of "munged name" for operands in C++ code.
    That is, "Ra.uq" will now be known in the C++ as "Ra"
    rather than "Ra_uq".  It wasn't legal to use different
    type extensions for the same operand at the same time
    anyway, and now it will be easier to refer to explicit
    operands in template code if necessary.

--HG--
extra : convert_revision : 9ff41e0201aeefe761743084ecdb34f4b9c84fdb
2006-02-09 14:51:37 -05:00
Gabe Black
5102de8321 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : ae574fbee484019d318ef25034bd4a7e18354aab
2006-02-09 14:48:10 -05:00
Gabe Black
ecfe2cc91f Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : 6b218e875e5c6299cd38727071e401a3e729266a
2006-02-09 14:37:44 -05:00
Gabe Black
7d9b93d825 Changed the filenames to the new standard again
arch/sparc/isa/formats.isa:
    Changed the file extensions to .isa again.
arch/sparc/isa/main.isa:
    Changed the file extensions to .isa again

--HG--
rename : arch/sparc/isa_desc/base.h => arch/sparc/isa/base.isa
rename : arch/sparc/isa_desc/bitfields.h => arch/sparc/isa/bitfields.isa
rename : arch/sparc/isa_desc/decoder.h => arch/sparc/isa/decoder.isa
rename : arch/sparc/isa_desc/formats.h => arch/sparc/isa/formats.isa
rename : arch/sparc/isa_desc/formats/basic.format => arch/sparc/isa/formats/basic.isa
rename : arch/sparc/isa_desc/formats/branch.format => arch/sparc/isa/formats/branch.isa
rename : arch/sparc/isa_desc/formats/integerop.format => arch/sparc/isa/formats/integerop.isa
rename : arch/sparc/isa_desc/formats/mem.format => arch/sparc/isa/formats/mem.isa
rename : arch/sparc/isa_desc/formats/noop.format => arch/sparc/isa/formats/noop.isa
rename : arch/sparc/isa_desc/formats/trap.format => arch/sparc/isa/formats/trap.isa
rename : arch/sparc/isa_desc/includes.h => arch/sparc/isa/includes.isa
rename : arch/sparc/isa_desc/isa_desc => arch/sparc/isa/main.isa
rename : arch/sparc/isa_desc/operands.h => arch/sparc/isa/operands.isa
extra : convert_revision : acb087e81d06ca5d67fe9b402423d7930f6ae798
2006-02-09 13:56:24 -05:00
Gabe Black
a0f65246bf Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 41a0e8c0b2d328bee958126f395369d4549aabfc
2006-02-09 13:07:00 -05:00
Gabe Black
d3c1cc9f15 A fix for SConscript so it will work with newer versions of scons
SConscript:
    Changed the ISAPath function to take 5 arguments to work with scons 0.97.

--HG--
extra : convert_revision : 34fbe131aec9349631b5026d839563380623f3fd
2006-02-09 13:06:47 -05:00
Korey Sewell
fb10300c4f more code for instructions... Mainly for coprocessor0 and coprocessor1 move instructions
--HG--
extra : convert_revision : 34e017fd0a6f330f2ac17d34af216fc14f09dd42
2006-02-09 04:26:04 -05:00
Korey Sewell
710b894351 Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 2bfc19cfa186776ff94440b01ea51f520f61234f
2006-02-08 16:24:25 -05:00
Korey Sewell
b6d21b7a34 Code for more "BasicOp" instructions ... formats for all instructions in place ... Edits to Branch Format
arch/mips/isa/decoder.isa:
    Code for di,ei,seb,seh,clz,and clo ....

    Every instruction has a format now (of course these are initial formats are still subject to change!)
arch/mips/isa/formats/branch.isa:
    Format Branch in MIPS similar to Alpha Format

--HG--
extra : convert_revision : 2118a1d9668610b1e9f1dea66d878b7b36c1ac7e
2006-02-08 16:24:04 -05:00
Korey Sewell
b203d7bd33 add at least BasicOp Format to most if not all instructions
and file name changes ...

arch/mips/isa/decoder.isa:
    add at least BasicOp Format to most if not all instructions

--HG--
rename : arch/mips/isa/formats/basic.format => arch/mips/isa/formats/basic.isa
rename : arch/mips/isa/formats/branch.format => arch/mips/isa/formats/branch.isa
rename : arch/mips/isa/formats/fp.format => arch/mips/isa/formats/fp.isa
rename : arch/mips/isa/formats/int.format => arch/mips/isa/formats/int.isa
rename : arch/mips/isa/formats/mem.format => arch/mips/isa/formats/mem.isa
rename : arch/mips/isa/formats/noop.format => arch/mips/isa/formats/noop.isa
rename : arch/mips/isa/formats/tlbop.format => arch/mips/isa/formats/tlbop.isa
rename : arch/mips/isa/formats/trap.format => arch/mips/isa/formats/trap.isa
rename : arch/mips/isa/mips.isa => arch/mips/isa/main.isa
extra : convert_revision : 0b2f3aee13fee3e0e25c0c746af4216c4a596391
2006-02-08 14:50:07 -05:00
Steve Reinhardt
524da7cd20 Replace ad-hoc or locally defined power-of-2 tests
with isPowerOf2() from intmath.hh.

base/sched_list.hh:
    Use isPowerOf2() from intmath.hh.

--HG--
extra : convert_revision : 7b2409531d8ed194aa7e1cfcd1ecb8460c797a16
2006-02-08 10:40:43 -05:00
Gabe Black
f444a7e799 Moved the alpha isa_desc to conform to the new naming system.
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
extra : convert_revision : a3cc14c202ae606db270c2c29847170d90c05216
2006-02-08 02:17:47 -05:00
Gabe Black
e59fdcdd39 Some fixups
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    Replaced the namespace declaration with including arch/alpha/isa_traits.hh

--HG--
extra : convert_revision : 07cb73a9f30f0e165809668f9baff6a3e3f94580
2006-02-08 01:57:47 -05:00
Gabe Black
29bc6c086a Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : c7caf571575fb0e7136770864371300d3f11787e
2006-02-08 01:04:32 -05:00
Gabe Black
82f2ae56ed Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh
SConscript:
    Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
    Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
    Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
    Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
    Added MIPS as a valid architecture
cpu/exec_context.hh:
    Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.

--HG--
extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007
2006-02-08 01:03:55 -05:00
Korey Sewell
7219693f4c Actually we do need a separate class for Integer Ops with Immediates!!!
The extra class is needed because of the necessisty of an immediate member variable.

Also, added some 'very modest' python code to choose between the IntOp and
the IntImmOp based on the instruction name ...

--HG--
extra : convert_revision : f109c12418202a99b40e270360134e8335739836
2006-02-07 19:28:19 -05:00