sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
3455 commits 2 branches 0 tags 204 MiB
Commit graph

3455 commits

This branch
This branch
All branches
Author SHA1 Message Date
Gabe Black 45368c0300 Fix stupid typo 
--HG--
extra : convert_revision : fbfc82974e89b2c726b689674c9f5d957682b280
 2006-10-31 18:01:31 -05:00
Gabe Black fb5ba85abb Make two simple utility functions to determine if a MiscReg index corresponding to an IPR is readable or writable. 
--HG--
extra : convert_revision : 89eebba5eec01e629213997d24c734a6acad0ecb
 2006-10-31 17:50:57 -05:00
Gabe Black 312a4710d7 Forgot to add intr_flag in one place. 
--HG--
extra : convert_revision : 637256098e2283c18f98bdaabf21f3039d162a15
 2006-10-31 17:14:46 -05:00
Gabe Black ad201172c9 We don't include ipr.cc in SE builds, so don't call it. 
--HG--
extra : convert_revision : 45e52d7afbf74e0ddde11f58aeb084186389fc06
 2006-10-31 16:59:41 -05:00
Gabe Black ace4f0c188 Made the old name refer to the miscreg index to prevent having to change code all over the place. 
--HG--
extra : convert_revision : e890a3ce420336acdb220396dcbf66d4b9974c76
 2006-10-31 16:36:45 -05:00
Gabe Black 44f2c05118 Forgot to change the index. 
--HG--
extra : convert_revision : 5a444e635d20bcca445a10e43592b6c10d25e879
 2006-10-31 16:18:54 -05:00
Gabe Black ece796ab8a Make the IPRs use regular miscreg indexes, and make a table or two to find the miscreg index of a specific IPR. 
--HG--
extra : convert_revision : dd235261e7086d6667b1b2bdc4a81b2573e21d53
 2006-10-31 16:02:28 -05:00
Gabe Black 3c19c5f0f2 Missed a few instances of this function. 
--HG--
extra : convert_revision : 581f97dafc2b30bd5067f6ff7f9cdbabc6890622
 2006-10-31 04:12:52 -05:00
Gabe Black eab445e1bc Get rid of old, commented out code. 
--HG--
extra : convert_revision : 46e9f26917efab642b80ea9e4303ec95d43d935e
 2006-10-31 03:44:39 -05:00
Gabe Black 038217049a Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions. 
--HG--
extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
 2006-10-31 03:37:01 -05:00
Gabe Black 4862879a94 Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes more neutral names. 
--HG--
extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4
 2006-10-31 02:08:44 -05:00
Steve Reinhardt 79d4bede42 Delete obsolete directories: src/oldmem, src/mem/timing, src/mem/NOTES. 
--HG--
extra : convert_revision : 948b4aaf484f7f7c2fce16201cd51ecb111af7d4
 2006-10-30 23:53:20 -05:00
Lisa Hsu 697b432ba8 FSConfig.py: 
Accidentally committed this last time

configs/common/FSConfig.py:
    Accidentally committed this last time

--HG--
extra : convert_revision : 32d49c17c661b57a9aa9c3b057258f6e037ba745
 2006-10-30 16:55:52 -05:00
Lisa Hsu 580c8421ab se.py, fs.py: 
import Caches
Simulation.py:
Fix typo - L2Cache --> L1Cache

configs/common/Simulation.py:
    Fix typo - L2Cache --> L1Cache
configs/example/fs.py:
configs/example/se.py:
    import Caches

--HG--
extra : convert_revision : 4292225b322c069665262eab7c83b5341844fba0
 2006-10-30 16:51:46 -05:00
Lisa Hsu fe2698c435 ensure that there is a "/" between the cptdir and the cpt.%d. 
--HG--
extra : convert_revision : 9aed7c3aecad10b039f3cfb26e04a7950be6bed1
 2006-10-30 14:19:16 -05:00
Lisa Hsu 13cbd4e94b Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 836fcb45f399ed4f860be2d0bfe2ac4709bfe2ef
 2006-10-30 14:15:50 -05:00
Lisa Hsu 883f0394f5 decouple the switch option from the warmup period option - parsing was confused otherwise, oops. 
--HG--
extra : convert_revision : 951fc664c59363df5f5e026aa791d83c26f050ec
 2006-10-30 14:12:15 -05:00
Kevin Lim bc93802fb8 Use some python os.path stuff to make it more flexible where we can execute this script from. 
--HG--
extra : convert_revision : a76861a0f2669a7cd3bf3a34177739c69a913545
 2006-10-30 14:01:34 -05:00
Lisa Hsu 9be53b10b3 Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : ce5f394a4a62f7452b9631763425f65b911387bb
 2006-10-30 13:33:38 -05:00
Lisa Hsu b40af2328a add some comments and make the warmup period in a switchover parameterizable. 
configs/common/Options.py:
    make the warmup period in a standard switch part of the option.
configs/common/Simulation.py:
    add some comments and also make the warmup period an option.

--HG--
extra : convert_revision : 0fa587291b97ff87c3b3a617e7359ac6d9bed7a5
 2006-10-30 13:33:27 -05:00
Gabe Black 628a3b1d01 An attempt to serialize the state of the micro code mechanism in the simple cpu. 
src/cpu/simple/base.cc:
    Make a microcoded op start at the current micropc, rather than starting at 0.
src/cpu/thread_state.cc:
    Serialize the microPC and nextMicroPC

--HG--
extra : convert_revision : 5302215f17312ecef3ff4c6548acb05297ee4ff6
 2006-10-29 04:04:50 -05:00
Gabe Black 349c7aff9b Move the mem classes into util.isa so that multiple inheritance can be used in the future for micro insts. 
--HG--
extra : convert_revision : c71faa5e43b56ed15d00ed5fd57c020d1c845445
 2006-10-29 03:40:52 -05:00
Gabe Black 6e66de7c75 Fix when the IsDelayedCommit flag is set. 
--HG--
extra : convert_revision : ab6cd69f82b2013d66a91beaa3e39d8f417a9251
 2006-10-29 03:26:41 -05:00
Gabe Black 9adba8d98e Bring casa and casxa up to date 
src/arch/sparc/isa/decoder.isa:
    Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
    This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
    The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
    Reorganized things a bit to better support cas

--HG--
extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
 2006-10-29 02:57:32 -05:00
Gabe Black ce313a15d5 Fixed ldstub to use the right format, and made the load/store operations use the integer microcode register. 
--HG--
extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
 2006-10-29 01:59:30 -05:00
Gabe Black 6dddca9511 Add an integer microcode register. 
--HG--
extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
 2006-10-29 01:58:37 -05:00
Ali Saidi 61c808ae1c Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : df73fd850d6638cbce6ff31203857f51235b8763
 2006-10-28 13:17:05 -04:00
Ali Saidi 14f53b9b6b remove intel nic from SConscript 
--HG--
extra : convert_revision : b01bb258c97cf42d46a94faedab31726623fe437
 2006-10-28 13:16:53 -04:00
Gabe Black ab6b6a9202 This one really needs to be arch/faults.hh 
--HG--
extra : convert_revision : aad1ee04ade9f4394c9ef0386f23d6f2ca373412
 2006-10-28 04:44:05 -04:00
Gabe Black 7f1463f94a Include the right version of faults.hh 
--HG--
extra : convert_revision : 4762b8ab46ac755726cc658a378c2cf5b2061dc3
 2006-10-28 04:00:24 -04:00
Gabe Black 477693c519 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 9883fb35fd9c36e1819153f9976f8bdc73dbe8f3
 2006-10-28 03:48:23 -04:00
Gabe Black 27ef642a76 One last adjustment to get rid of skew in the simple atomic cpu. 
--HG--
extra : convert_revision : 8e46929ed7da5dae6888f773de4e1ecc9b249fe0
 2006-10-28 03:44:55 -04:00
Lisa Hsu 2305490de5 Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

configs/example/fs.py:
configs/example/se.py:
    hand merge

--HG--
extra : convert_revision : 13d248add87ac373d2653bb42adf4ac065f75ce3
 2006-10-27 16:40:06 -04:00
Lisa Hsu a6fd29ddf9 factor out common run code from se.py and fs.py. 
configs/example/fs.py:
    factor out common code.
configs/example/se.py:
    factor out common code

--HG--
extra : convert_revision : 72a1f653c84eae1b7d281e0a5e60ee116ad6b27d
 2006-10-27 16:32:26 -04:00
Ali Saidi 8a0c79a315 Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : b8b8a4428b2462d2df600e2ec7a9014a08246df8
 2006-10-27 09:11:02 -04:00
Ali Saidi baaadb0d43 add packet_access.hh 
--HG--
extra : convert_revision : 7fe4958549101fca9613baa4a317d96f4970d432
 2006-10-27 09:10:50 -04:00
Gabe Black a46e19f738 A more complete attempt to fix the clock skew. 
--HG--
extra : convert_revision : b2d505de51fc5fcae5177b2a13140729474e249e
 2006-10-27 07:09:14 -04:00
Gabe Black d5974eff73 Potential fix to clock skew problem. 
--HG--
extra : convert_revision : 51572523190a886fd0ff64817edc88e260c5fa9d
 2006-10-27 06:51:28 -04:00
Gabe Black f985b752d3 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : ec35a9276ae21e0b9fe820bd700c020e4440a350
 2006-10-27 02:34:26 -04:00
Gabe Black ca34c62bf9 Update stats for fill/spill handlers 
--HG--
extra : convert_revision : 2ed2e868ccbb3316f84ea691497d2e0dd4ec2416
 2006-10-27 02:21:09 -04:00
Gabe Black 709d50cd6b Got rid of some outdated comments. 
--HG--
extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
 2006-10-27 01:43:51 -04:00
Gabe Black b1cc98ed54 Made the regfile compatible with the new definitions in MiscRegFile 
--HG--
extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
 2006-10-27 01:43:26 -04:00
Gabe Black 944bfde6b3 Clean up MiscRegFile 
--HG--
extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
 2006-10-27 01:36:42 -04:00
Gabe Black 2cb190d1e3 Reorganized the MiscRegFile 
--HG--
extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2
 2006-10-26 22:48:02 -04:00
Gabe Black f33bab2386 Cleaned up the decoder slightly. 
--HG--
extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
 2006-10-26 22:47:17 -04:00
Gabe Black f88b90dd56 Added a few functions to stuff values into bitfields in an instruction. 
--HG--
extra : convert_revision : 507d7e13fd6276acf36b75eba31dff5e8080113f
 2006-10-26 20:25:22 -04:00
Gabe Black d1b30102fd Changed the number of register windows to be more realistic. 
--HG--
extra : convert_revision : ae557307f377b19bae82226dafa8b4b2654cae52
 2006-10-26 20:24:01 -04:00
Gabe Black 5024b20278 Got rid of some debug output 
--HG--
extra : convert_revision : 6e98cf839dc92bde5f06f9b9bf11ca6ac661c907
 2006-10-26 20:23:00 -04:00
Gabe Black e441be1b82 Change the default function from setMiscRegWithEffect to setMiscReg 
--HG--
extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
 2006-10-26 20:22:23 -04:00
Lisa Hsu 2f30c2b4c9 Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/clean

--HG--
extra : convert_revision : cb3f718bdcbd52540747a2696fb37bb4fcfe27a3
 2006-10-26 16:04:27 -04:00