Gabe Black
44e912c6bd
X86: Explain what really didn't work with unmapped addresses in SE mode.
2009-11-08 22:49:57 -08:00
Steve Reinhardt
1c28004654
Clean up some inconsistencies with Request flags.
2009-08-01 22:50:13 -07:00
Gabe Black
0cb180ea0d
Registers: Eliminate the ISA defined floating point register file.
2009-07-08 23:02:20 -07:00
Gabe Black
32daf6fc3f
Registers: Add an ISA object which replaces the MiscRegFile.
...
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
2009-07-08 23:02:20 -07:00
Gabe Black
b6bfe8af26
X86: Split out the internal memory space from the regular translate() and precompute mode.
2009-04-26 16:48:44 -07:00
Gabe Black
ee7055c289
X86: Put the StoreCheck flag with the others, and don't collide with other flags.
2009-04-23 01:43:00 -07:00
Gabe Black
6910baa015
X86: Fix how the TLB handles the storecheck flag.
2009-04-19 04:57:51 -07:00
Gabe Black
3b1b21cb15
X86: Some segment selectors can be used when "NULL".
2009-04-19 03:41:10 -07:00
Nathan Binkert
e0de2c3443
tlb: More fixing of unified TLB
2009-04-08 22:21:27 -07:00
Gabe Black
7b5a96f06b
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
2009-04-08 22:21:27 -07:00
Nathan Binkert
4523741c1c
quell gcc 4.3 warning
2009-02-27 17:29:58 -08:00
Gabe Black
9dfa3f7f73
X86: Fix segment limit checks.
2009-02-27 09:23:50 -08:00
Gabe Black
c849ef58c0
X86: Actually check page protections.
2009-02-25 10:18:58 -08:00
Gabe Black
dc53ca89f6
X86: Add a flag to force memory accesses to happen at CPL 0.
2009-02-25 10:18:22 -08:00
Gabe Black
40fdba2454
X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults.
2009-02-25 10:16:21 -08:00
Gabe Black
6ed47e9464
CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.
2009-02-25 10:16:15 -08:00
Gabe Black
5605079b1f
ISA: Replace the translate functions in the TLBs with translateAtomic.
2009-02-25 10:15:44 -08:00
Gabe Black
e8c1c3e72e
X86: Pass whether an access was a read/write/fetch so faults can behave accordingly.
2009-02-23 00:20:34 -08:00
Gabe Black
06cdbe5ea7
X86: Compute PCI config addresses correctly.
2009-02-01 00:11:49 -08:00
Nathan Binkert
9c49bc7b00
mem: update stuff for changes to Packet and Request
2008-11-10 11:51:17 -08:00
Lisa Hsu
d857faf073
Add in Context IDs to the simulator. From now on, cpuId is almost never used,
...
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
2008-11-02 21:57:07 -05:00
Lisa Hsu
c55a467a06
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
...
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
2008-11-02 21:56:57 -05:00
Gabe Black
42ebebf99a
X86: Make the local APIC accessible through the memory system directly, and make the timer work.
2008-10-12 11:08:00 -07:00
Gabe Black
d9f9c967fb
Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
2008-10-12 09:09:56 -07:00
Gabe Black
6b8d0363ee
X86: Rename the divide count register to divide configuration.
2008-06-12 00:54:12 -04:00
Gabe Black
66f54a6037
X86: Change how segment loading is performed.
2008-06-12 00:52:12 -04:00
Gabe Black
b05299253f
X86: In non 64bit mode, throw a fault when a NULL segment is accessed.
2008-06-12 00:51:50 -04:00
Gabe Black
8688ef3fe5
X86: Have all 8 machine check registers since the kernel assumes they're there.
2008-06-12 00:48:02 -04:00
Gabe Black
a8e3001df8
X86: Bypass unaligned access support for register addressed MSRs.
2008-06-12 00:47:25 -04:00
Gabe Black
b3e55339f9
X86: Remove enforcement of APIC register access alignment. Panic if more than one register is accessed at a time.
2008-06-12 00:46:22 -04:00
Gabe Black
66aaabf4ae
X86: Don't map the local APIC into the physical address space in SE mode.
...
--HG--
extra : convert_revision : b7103974b12130bbf43583c4cb5294b808add208
2008-03-01 00:05:12 -05:00
Gabe Black
43ecce5fda
X86: Put in initial implementation of the local APIC.
...
--HG--
extra : convert_revision : 1708a93d96b819e64ed456c75dbb5325ac8114a8
2008-02-26 23:39:53 -05:00
Gabe Black
98d2ca403e
X86: Implement the INVLPG instruction and the TIA microop.
...
--HG--
extra : convert_revision : 31db1ee082f6c3ca5443cba1eb335e408661ead2
2008-02-26 23:39:22 -05:00
Gabe Black
8b4796a367
TLB: Make a TLB base class and put a virtual demapPage function in it.
...
--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
2008-02-26 23:38:51 -05:00
Gabe Black
7bde0285e5
X86: Get PCI config space to work, and adjust address space prefix numbering scheme.
...
--HG--
extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
2008-02-26 23:38:01 -05:00
Gabe Black
223e48e6ae
X86: Make the IO ports work using extra physical address lines. Add a serial port.
...
--HG--
extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
2008-01-12 06:39:15 -05:00
Gabe Black
dc6f960171
X86: Reorganize segmentation and implement segment selector movs.
...
--HG--
extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8
2007-12-01 23:03:39 -08:00
Gabe Black
1048b548fa
X86: Separate out the page table walker into it's own cc and hh.
...
--HG--
extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042
2007-11-12 18:06:57 -08:00
Gabe Black
917ae9ec66
X86: Fix a stupid typo where WRMSR and RDMSR were switched, and add a debug statement.
...
--HG--
extra : convert_revision : f1eb17291f4c01f3c0fa8f99650bc1edf09d21de
2007-11-12 14:39:14 -08:00
Gabe Black
4950798268
X86: Implement tlb invalidation and make it happen some of the times it should.
...
--HG--
extra : convert_revision : 376516d33cd539fa526c834ef2b2c33069af3040
2007-11-12 14:39:07 -08:00
Gabe Black
fce45baf17
X86: Work on the page table walker, TLB, and related faults.
...
--HG--
extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
2007-11-12 14:38:31 -08:00
Gabe Black
f17f3d20be
X86: Implement a page table walker.
...
--HG--
extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
2007-11-12 14:38:24 -08:00
Gabe Black
aaa30714b3
X86: Various fixes to indexing segmentation related registers
...
--HG--
extra : convert_revision : 3d45da3a3fb38327582cfdfb72cfc4ce1b1d31af
2007-11-12 14:37:54 -08:00
Gabe Black
fddfa71658
TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.
...
--HG--
extra : convert_revision : 2421af11f62f60fb48faeee6bddadac2987df0e8
2007-10-25 19:04:44 -07:00
Gabe Black
9498e536c0
X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
...
There are no priviledge checks, so these instructions will all work in all
modes.
--HG--
extra : convert_revision : ff893eb569313d8aecbfffb47bcbd1c2d65cd393
2007-10-12 16:37:55 -07:00
Gabe Black
a19c212757
X86: Work on the x86 tlb.
...
--HG--
extra : convert_revision : a08a5cb049a6030ba9fd56a89383d56026238dbf
2007-10-07 18:18:39 -07:00
Gabe Black
50e2d20cb8
Merge with head.
...
--HG--
extra : convert_revision : 1aa0e4569a7c10e6a395c2c951ac29275b5bcf59
2007-10-02 23:03:38 -07:00
Gabe Black
504f90f763
X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.
...
--HG--
extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af
2007-10-02 23:00:37 -07:00
Ali Saidi
d325f49b70
Rename cycles() function to ticks()
...
--HG--
extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
2007-09-28 13:21:52 -04:00
Gabe Black
418ddf43e6
X86: Get X86_FS to compile.
...
--HG--
extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01
2007-09-24 17:39:56 -07:00