859 lines
27 KiB
C++
859 lines
27 KiB
C++
/*
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* Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use of this software in source and binary forms,
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* with or without modification, are permitted provided that the
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* following conditions are met:
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*
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* The software must be used only for Non-Commercial Use which means any
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* use which is NOT directed to receiving any direct monetary
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* compensation for, or commercial advantage from such use. Illustrative
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* examples of non-commercial use are academic research, personal study,
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* teaching, education and corporate research & development.
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* Illustrative examples of commercial use are distributing products for
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* commercial advantage and providing services using the software for
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* commercial advantage.
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*
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* If you wish to use this software or functionality therein that may be
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* covered by patents for commercial use, please contact:
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* Director of Intellectual Property Licensing
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* Office of Strategy and Technology
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* Hewlett-Packard Company
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* 1501 Page Mill Road
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* Palo Alto, California 94304
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*
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* Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer. Redistributions
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* in binary form must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution. Neither the name of
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* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission. No right of
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* sublicense is granted herewith. Derivatives of the software and
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* output created using the software may be prepared, but only for
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* Non-Commercial Uses. Derivatives of the software may be shared with
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* others provided: (i) the others agree to abide by the list of
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* conditions herein which includes the Non-Commercial Use restrictions;
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* and (ii) such Derivatives of the software include the above copyright
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* notice to acknowledge the contribution from this software where
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* applicable, this list of conditions and the disclaimer below.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include <cstring>
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#include "config/full_system.hh"
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#include "arch/x86/pagetable.hh"
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#include "arch/x86/tlb.hh"
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#include "arch/x86/x86_traits.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/base.hh"
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#include "mem/packet_access.hh"
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#include "mem/request.hh"
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#if FULL_SYSTEM
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#include "arch/x86/pagetable_walker.hh"
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#endif
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namespace X86ISA {
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TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
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{
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tlb = new TlbEntry[size];
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std::memset(tlb, 0, sizeof(TlbEntry) * size);
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for (int x = 0; x < size; x++)
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freeList.push_back(&tlb[x]);
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#if FULL_SYSTEM
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walker = p->walker;
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walker->setTLB(this);
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#endif
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}
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void
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TLB::insert(Addr vpn, TlbEntry &entry)
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{
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//TODO Deal with conflicting entries
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TlbEntry *newEntry = NULL;
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if (!freeList.empty()) {
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newEntry = freeList.front();
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freeList.pop_front();
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} else {
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newEntry = entryList.back();
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entryList.pop_back();
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}
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*newEntry = entry;
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newEntry->vaddr = vpn;
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entryList.push_front(newEntry);
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}
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TLB::EntryList::iterator
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TLB::lookupIt(Addr va, bool update_lru)
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{
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//TODO make this smarter at some point
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EntryList::iterator entry;
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for (entry = entryList.begin(); entry != entryList.end(); entry++) {
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if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
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DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
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"with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
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if (update_lru) {
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entryList.push_front(*entry);
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entryList.erase(entry);
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entry = entryList.begin();
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}
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break;
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}
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}
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return entry;
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}
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TlbEntry *
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TLB::lookup(Addr va, bool update_lru)
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{
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EntryList::iterator entry = lookupIt(va, update_lru);
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if (entry == entryList.end())
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return NULL;
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else
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return *entry;
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}
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#if FULL_SYSTEM
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void
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TLB::walk(ThreadContext * _tc, Addr vaddr)
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{
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walker->start(_tc, vaddr);
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}
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#endif
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void
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TLB::invalidateAll()
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{
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DPRINTF(TLB, "Invalidating all entries.\n");
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while (!entryList.empty()) {
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TlbEntry *entry = entryList.front();
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entryList.pop_front();
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freeList.push_back(entry);
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}
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}
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void
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TLB::setConfigAddress(uint32_t addr)
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{
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configAddress = addr;
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}
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void
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TLB::invalidateNonGlobal()
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{
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DPRINTF(TLB, "Invalidating all non global entries.\n");
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EntryList::iterator entryIt;
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for (entryIt = entryList.begin(); entryIt != entryList.end();) {
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if (!(*entryIt)->global) {
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freeList.push_back(*entryIt);
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entryList.erase(entryIt++);
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} else {
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entryIt++;
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}
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}
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}
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void
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TLB::demapPage(Addr va, uint64_t asn)
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{
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EntryList::iterator entry = lookupIt(va, false);
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if (entry != entryList.end()) {
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freeList.push_back(*entry);
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entryList.erase(entry);
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}
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}
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template<class TlbFault>
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Fault
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TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
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{
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Addr vaddr = req->getVaddr();
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DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
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uint32_t flags = req->getFlags();
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bool storeCheck = flags & StoreCheck;
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int seg = flags & mask(4);
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//XXX Junk code to surpress the warning
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if (storeCheck);
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// If this is true, we're dealing with a request to read an internal
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// value.
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if (seg == SEGMENT_REG_MS) {
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DPRINTF(TLB, "Addresses references internal memory.\n");
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Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
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if (prefix == IntAddrPrefixCPUID) {
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panic("CPUID memory space not yet implemented!\n");
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} else if (prefix == IntAddrPrefixMSR) {
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vaddr = vaddr >> 3;
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req->setMmapedIpr(true);
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Addr regNum = 0;
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switch (vaddr & ~IntAddrPrefixMask) {
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case 0x10:
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regNum = MISCREG_TSC;
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break;
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case 0x1B:
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regNum = MISCREG_APIC_BASE;
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break;
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case 0xFE:
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regNum = MISCREG_MTRRCAP;
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break;
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case 0x174:
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regNum = MISCREG_SYSENTER_CS;
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break;
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case 0x175:
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regNum = MISCREG_SYSENTER_ESP;
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break;
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case 0x176:
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regNum = MISCREG_SYSENTER_EIP;
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break;
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case 0x179:
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regNum = MISCREG_MCG_CAP;
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break;
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case 0x17A:
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regNum = MISCREG_MCG_STATUS;
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break;
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case 0x17B:
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regNum = MISCREG_MCG_CTL;
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break;
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case 0x1D9:
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regNum = MISCREG_DEBUG_CTL_MSR;
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break;
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case 0x1DB:
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regNum = MISCREG_LAST_BRANCH_FROM_IP;
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break;
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case 0x1DC:
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regNum = MISCREG_LAST_BRANCH_TO_IP;
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break;
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case 0x1DD:
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regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
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break;
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case 0x1DE:
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regNum = MISCREG_LAST_EXCEPTION_TO_IP;
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break;
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case 0x200:
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regNum = MISCREG_MTRR_PHYS_BASE_0;
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break;
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case 0x201:
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regNum = MISCREG_MTRR_PHYS_MASK_0;
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break;
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case 0x202:
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regNum = MISCREG_MTRR_PHYS_BASE_1;
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break;
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case 0x203:
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regNum = MISCREG_MTRR_PHYS_MASK_1;
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break;
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case 0x204:
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regNum = MISCREG_MTRR_PHYS_BASE_2;
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break;
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case 0x205:
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regNum = MISCREG_MTRR_PHYS_MASK_2;
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break;
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case 0x206:
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regNum = MISCREG_MTRR_PHYS_BASE_3;
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break;
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case 0x207:
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regNum = MISCREG_MTRR_PHYS_MASK_3;
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break;
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case 0x208:
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regNum = MISCREG_MTRR_PHYS_BASE_4;
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break;
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case 0x209:
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regNum = MISCREG_MTRR_PHYS_MASK_4;
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break;
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case 0x20A:
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regNum = MISCREG_MTRR_PHYS_BASE_5;
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break;
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case 0x20B:
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regNum = MISCREG_MTRR_PHYS_MASK_5;
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break;
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case 0x20C:
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regNum = MISCREG_MTRR_PHYS_BASE_6;
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break;
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case 0x20D:
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regNum = MISCREG_MTRR_PHYS_MASK_6;
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break;
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case 0x20E:
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regNum = MISCREG_MTRR_PHYS_BASE_7;
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break;
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case 0x20F:
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regNum = MISCREG_MTRR_PHYS_MASK_7;
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break;
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case 0x250:
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regNum = MISCREG_MTRR_FIX_64K_00000;
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break;
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case 0x258:
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regNum = MISCREG_MTRR_FIX_16K_80000;
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break;
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case 0x259:
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regNum = MISCREG_MTRR_FIX_16K_A0000;
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break;
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case 0x268:
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regNum = MISCREG_MTRR_FIX_4K_C0000;
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break;
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case 0x269:
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regNum = MISCREG_MTRR_FIX_4K_C8000;
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break;
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case 0x26A:
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regNum = MISCREG_MTRR_FIX_4K_D0000;
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break;
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case 0x26B:
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regNum = MISCREG_MTRR_FIX_4K_D8000;
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break;
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case 0x26C:
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regNum = MISCREG_MTRR_FIX_4K_E0000;
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break;
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case 0x26D:
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regNum = MISCREG_MTRR_FIX_4K_E8000;
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break;
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case 0x26E:
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regNum = MISCREG_MTRR_FIX_4K_F0000;
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break;
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case 0x26F:
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regNum = MISCREG_MTRR_FIX_4K_F8000;
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break;
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case 0x277:
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regNum = MISCREG_PAT;
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break;
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case 0x2FF:
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regNum = MISCREG_DEF_TYPE;
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break;
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case 0x400:
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regNum = MISCREG_MC0_CTL;
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break;
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case 0x404:
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regNum = MISCREG_MC1_CTL;
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break;
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case 0x408:
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regNum = MISCREG_MC2_CTL;
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break;
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case 0x40C:
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regNum = MISCREG_MC3_CTL;
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break;
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case 0x410:
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regNum = MISCREG_MC4_CTL;
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break;
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case 0x414:
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regNum = MISCREG_MC5_CTL;
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break;
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case 0x418:
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regNum = MISCREG_MC6_CTL;
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break;
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case 0x41C:
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regNum = MISCREG_MC7_CTL;
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break;
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case 0x401:
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regNum = MISCREG_MC0_STATUS;
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break;
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case 0x405:
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regNum = MISCREG_MC1_STATUS;
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break;
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case 0x409:
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regNum = MISCREG_MC2_STATUS;
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break;
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case 0x40D:
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regNum = MISCREG_MC3_STATUS;
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break;
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case 0x411:
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regNum = MISCREG_MC4_STATUS;
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break;
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case 0x415:
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regNum = MISCREG_MC5_STATUS;
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break;
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case 0x419:
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regNum = MISCREG_MC6_STATUS;
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break;
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case 0x41D:
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regNum = MISCREG_MC7_STATUS;
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break;
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case 0x402:
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regNum = MISCREG_MC0_ADDR;
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break;
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case 0x406:
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regNum = MISCREG_MC1_ADDR;
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break;
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case 0x40A:
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regNum = MISCREG_MC2_ADDR;
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break;
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case 0x40E:
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regNum = MISCREG_MC3_ADDR;
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break;
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case 0x412:
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regNum = MISCREG_MC4_ADDR;
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break;
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case 0x416:
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regNum = MISCREG_MC5_ADDR;
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break;
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case 0x41A:
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regNum = MISCREG_MC6_ADDR;
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break;
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case 0x41E:
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regNum = MISCREG_MC7_ADDR;
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break;
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case 0x403:
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regNum = MISCREG_MC0_MISC;
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break;
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case 0x407:
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regNum = MISCREG_MC1_MISC;
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break;
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case 0x40B:
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regNum = MISCREG_MC2_MISC;
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break;
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case 0x40F:
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regNum = MISCREG_MC3_MISC;
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break;
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case 0x413:
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regNum = MISCREG_MC4_MISC;
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break;
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case 0x417:
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regNum = MISCREG_MC5_MISC;
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break;
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case 0x41B:
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regNum = MISCREG_MC6_MISC;
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break;
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case 0x41F:
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regNum = MISCREG_MC7_MISC;
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break;
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case 0xC0000080:
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regNum = MISCREG_EFER;
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break;
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case 0xC0000081:
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regNum = MISCREG_STAR;
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break;
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case 0xC0000082:
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regNum = MISCREG_LSTAR;
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break;
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case 0xC0000083:
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regNum = MISCREG_CSTAR;
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break;
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case 0xC0000084:
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regNum = MISCREG_SF_MASK;
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break;
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case 0xC0000100:
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regNum = MISCREG_FS_BASE;
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break;
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case 0xC0000101:
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regNum = MISCREG_GS_BASE;
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break;
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case 0xC0000102:
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regNum = MISCREG_KERNEL_GS_BASE;
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break;
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case 0xC0000103:
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regNum = MISCREG_TSC_AUX;
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break;
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case 0xC0010000:
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regNum = MISCREG_PERF_EVT_SEL0;
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break;
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case 0xC0010001:
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regNum = MISCREG_PERF_EVT_SEL1;
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break;
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case 0xC0010002:
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regNum = MISCREG_PERF_EVT_SEL2;
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break;
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case 0xC0010003:
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regNum = MISCREG_PERF_EVT_SEL3;
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break;
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case 0xC0010004:
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regNum = MISCREG_PERF_EVT_CTR0;
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break;
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case 0xC0010005:
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regNum = MISCREG_PERF_EVT_CTR1;
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break;
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case 0xC0010006:
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regNum = MISCREG_PERF_EVT_CTR2;
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break;
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case 0xC0010007:
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regNum = MISCREG_PERF_EVT_CTR3;
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break;
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case 0xC0010010:
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regNum = MISCREG_SYSCFG;
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break;
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case 0xC0010016:
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regNum = MISCREG_IORR_BASE0;
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break;
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case 0xC0010017:
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regNum = MISCREG_IORR_BASE1;
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break;
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case 0xC0010018:
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regNum = MISCREG_IORR_MASK0;
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break;
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case 0xC0010019:
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regNum = MISCREG_IORR_MASK1;
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break;
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case 0xC001001A:
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regNum = MISCREG_TOP_MEM;
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break;
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case 0xC001001D:
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regNum = MISCREG_TOP_MEM2;
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break;
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case 0xC0010114:
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regNum = MISCREG_VM_CR;
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break;
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case 0xC0010115:
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regNum = MISCREG_IGNNE;
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break;
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case 0xC0010116:
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regNum = MISCREG_SMM_CTL;
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break;
|
|
case 0xC0010117:
|
|
regNum = MISCREG_VM_HSAVE_PA;
|
|
break;
|
|
default:
|
|
return new GeneralProtection(0);
|
|
}
|
|
//The index is multiplied by the size of a MiscReg so that
|
|
//any memory dependence calculations will not see these as
|
|
//overlapping.
|
|
req->setPaddr(regNum * sizeof(MiscReg));
|
|
return NoFault;
|
|
} else if (prefix == IntAddrPrefixIO) {
|
|
// TODO If CPL > IOPL or in virtual mode, check the I/O permission
|
|
// bitmap in the TSS.
|
|
|
|
Addr IOPort = vaddr & ~IntAddrPrefixMask;
|
|
// Make sure the address fits in the expected 16 bit IO address
|
|
// space.
|
|
assert(!(IOPort & ~0xFFFF));
|
|
if (IOPort == 0xCF8 && req->getSize() == 4) {
|
|
req->setMmapedIpr(true);
|
|
req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
|
|
} else if ((IOPort & ~mask(2)) == 0xCFC) {
|
|
Addr configAddress =
|
|
tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
|
|
if (bits(configAddress, 31, 31)) {
|
|
req->setPaddr(PhysAddrPrefixPciConfig |
|
|
bits(configAddress, 30, 0));
|
|
}
|
|
} else {
|
|
req->setPaddr(PhysAddrPrefixIO | IOPort);
|
|
}
|
|
return NoFault;
|
|
} else {
|
|
panic("Access to unrecognized internal address space %#x.\n",
|
|
prefix);
|
|
}
|
|
}
|
|
|
|
// Get cr0. This will tell us how to do translation. We'll assume it was
|
|
// verified to be correct and consistent when set.
|
|
CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
|
|
|
|
// If protected mode has been enabled...
|
|
if (cr0.pe) {
|
|
DPRINTF(TLB, "In protected mode.\n");
|
|
Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
|
|
SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
|
|
// If we're not in 64-bit mode, do protection/limit checks
|
|
if (!efer.lma || !csAttr.longMode) {
|
|
DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
|
|
// Check for a NULL segment selector.
|
|
if (!tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
|
|
return new GeneralProtection(0);
|
|
bool expandDown = false;
|
|
if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
|
|
SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
|
|
if (!attr.writable && write)
|
|
return new GeneralProtection(0);
|
|
if (!attr.readable && !write && !execute)
|
|
return new GeneralProtection(0);
|
|
expandDown = attr.expandDown;
|
|
}
|
|
Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
|
|
Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
|
|
if (expandDown) {
|
|
DPRINTF(TLB, "Checking an expand down segment.\n");
|
|
// We don't have to worry about the access going around the
|
|
// end of memory because accesses will be broken up into
|
|
// pieces at boundaries aligned on sizes smaller than an
|
|
// entire address space. We do have to worry about the limit
|
|
// being less than the base.
|
|
if (limit < base) {
|
|
if (limit < vaddr + req->getSize() && vaddr < base)
|
|
return new GeneralProtection(0);
|
|
} else {
|
|
if (limit < vaddr + req->getSize())
|
|
return new GeneralProtection(0);
|
|
}
|
|
} else {
|
|
if (limit < base) {
|
|
if (vaddr <= limit || vaddr + req->getSize() >= base)
|
|
return new GeneralProtection(0);
|
|
} else {
|
|
if (vaddr <= limit && vaddr + req->getSize() >= base)
|
|
return new GeneralProtection(0);
|
|
}
|
|
}
|
|
}
|
|
// If paging is enabled, do the translation.
|
|
if (cr0.pg) {
|
|
DPRINTF(TLB, "Paging enabled.\n");
|
|
// The vaddr already has the segment base applied.
|
|
TlbEntry *entry = lookup(vaddr);
|
|
if (!entry) {
|
|
return new TlbFault(vaddr);
|
|
} else {
|
|
// Do paging protection checks.
|
|
DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr);
|
|
Addr paddr = entry->paddr | (vaddr & (entry->size-1));
|
|
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
|
|
req->setPaddr(paddr);
|
|
}
|
|
} else {
|
|
//Use the address which already has segmentation applied.
|
|
DPRINTF(TLB, "Paging disabled.\n");
|
|
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
|
|
req->setPaddr(vaddr);
|
|
}
|
|
} else {
|
|
// Real mode
|
|
DPRINTF(TLB, "In real mode.\n");
|
|
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
|
|
req->setPaddr(vaddr);
|
|
}
|
|
// Check for an access to the local APIC
|
|
#if FULL_SYSTEM
|
|
LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
|
|
Addr baseAddr = localApicBase.base << 12;
|
|
Addr paddr = req->getPaddr();
|
|
if (baseAddr <= paddr && baseAddr + (1 << 12) > paddr) {
|
|
req->setMmapedIpr(true);
|
|
// The Intel developer's manuals say the below restrictions apply,
|
|
// but the linux kernel, because of a compiler optimization, breaks
|
|
// them.
|
|
/*
|
|
// Check alignment
|
|
if (paddr & ((32/8) - 1))
|
|
return new GeneralProtection(0);
|
|
// Check access size
|
|
if (req->getSize() != (32/8))
|
|
return new GeneralProtection(0);
|
|
*/
|
|
|
|
//Make sure we're at least only accessing one register.
|
|
if ((paddr & ~mask(3)) != ((paddr + req->getSize()) & ~mask(3)))
|
|
panic("Accessed more than one register at a time in the APIC!\n");
|
|
MiscReg regNum;
|
|
Addr offset = paddr & mask(3);
|
|
paddr &= ~mask(3);
|
|
switch (paddr - baseAddr)
|
|
{
|
|
case 0x20:
|
|
regNum = MISCREG_APIC_ID;
|
|
break;
|
|
case 0x30:
|
|
regNum = MISCREG_APIC_VERSION;
|
|
break;
|
|
case 0x80:
|
|
regNum = MISCREG_APIC_TASK_PRIORITY;
|
|
break;
|
|
case 0x90:
|
|
regNum = MISCREG_APIC_ARBITRATION_PRIORITY;
|
|
break;
|
|
case 0xA0:
|
|
regNum = MISCREG_APIC_PROCESSOR_PRIORITY;
|
|
break;
|
|
case 0xB0:
|
|
regNum = MISCREG_APIC_EOI;
|
|
break;
|
|
case 0xD0:
|
|
regNum = MISCREG_APIC_LOGICAL_DESTINATION;
|
|
break;
|
|
case 0xE0:
|
|
regNum = MISCREG_APIC_DESTINATION_FORMAT;
|
|
break;
|
|
case 0xF0:
|
|
regNum = MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR;
|
|
break;
|
|
case 0x100:
|
|
case 0x108:
|
|
case 0x110:
|
|
case 0x118:
|
|
case 0x120:
|
|
case 0x128:
|
|
case 0x130:
|
|
case 0x138:
|
|
case 0x140:
|
|
case 0x148:
|
|
case 0x150:
|
|
case 0x158:
|
|
case 0x160:
|
|
case 0x168:
|
|
case 0x170:
|
|
case 0x178:
|
|
regNum = MISCREG_APIC_IN_SERVICE(
|
|
(paddr - baseAddr - 0x100) / 0x8);
|
|
break;
|
|
case 0x180:
|
|
case 0x188:
|
|
case 0x190:
|
|
case 0x198:
|
|
case 0x1A0:
|
|
case 0x1A8:
|
|
case 0x1B0:
|
|
case 0x1B8:
|
|
case 0x1C0:
|
|
case 0x1C8:
|
|
case 0x1D0:
|
|
case 0x1D8:
|
|
case 0x1E0:
|
|
case 0x1E8:
|
|
case 0x1F0:
|
|
case 0x1F8:
|
|
regNum = MISCREG_APIC_TRIGGER_MODE(
|
|
(paddr - baseAddr - 0x180) / 0x8);
|
|
break;
|
|
case 0x200:
|
|
case 0x208:
|
|
case 0x210:
|
|
case 0x218:
|
|
case 0x220:
|
|
case 0x228:
|
|
case 0x230:
|
|
case 0x238:
|
|
case 0x240:
|
|
case 0x248:
|
|
case 0x250:
|
|
case 0x258:
|
|
case 0x260:
|
|
case 0x268:
|
|
case 0x270:
|
|
case 0x278:
|
|
regNum = MISCREG_APIC_INTERRUPT_REQUEST(
|
|
(paddr - baseAddr - 0x200) / 0x8);
|
|
break;
|
|
case 0x280:
|
|
regNum = MISCREG_APIC_ERROR_STATUS;
|
|
break;
|
|
case 0x300:
|
|
regNum = MISCREG_APIC_INTERRUPT_COMMAND_LOW;
|
|
break;
|
|
case 0x310:
|
|
regNum = MISCREG_APIC_INTERRUPT_COMMAND_HIGH;
|
|
break;
|
|
case 0x320:
|
|
regNum = MISCREG_APIC_LVT_TIMER;
|
|
break;
|
|
case 0x330:
|
|
regNum = MISCREG_APIC_LVT_THERMAL_SENSOR;
|
|
break;
|
|
case 0x340:
|
|
regNum = MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
|
|
break;
|
|
case 0x350:
|
|
regNum = MISCREG_APIC_LVT_LINT0;
|
|
break;
|
|
case 0x360:
|
|
regNum = MISCREG_APIC_LVT_LINT1;
|
|
break;
|
|
case 0x370:
|
|
regNum = MISCREG_APIC_LVT_ERROR;
|
|
break;
|
|
case 0x380:
|
|
regNum = MISCREG_APIC_INITIAL_COUNT;
|
|
break;
|
|
case 0x390:
|
|
regNum = MISCREG_APIC_CURRENT_COUNT;
|
|
break;
|
|
case 0x3E0:
|
|
regNum = MISCREG_APIC_DIVIDE_CONFIGURATION;
|
|
break;
|
|
default:
|
|
// A reserved register field.
|
|
return new GeneralProtection(0);
|
|
break;
|
|
}
|
|
req->setPaddr(regNum * sizeof(MiscReg) + offset);
|
|
}
|
|
#endif
|
|
return NoFault;
|
|
};
|
|
|
|
Fault
|
|
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
|
|
{
|
|
return TLB::translate<FakeDTLBFault>(req, tc, write, false);
|
|
}
|
|
|
|
Fault
|
|
ITB::translate(RequestPtr &req, ThreadContext *tc)
|
|
{
|
|
return TLB::translate<FakeITLBFault>(req, tc, false, true);
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
Tick
|
|
DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
|
|
{
|
|
return tc->getCpuPtr()->ticks(1);
|
|
}
|
|
|
|
Tick
|
|
DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
|
|
{
|
|
return tc->getCpuPtr()->ticks(1);
|
|
}
|
|
|
|
#endif
|
|
|
|
void
|
|
TLB::serialize(std::ostream &os)
|
|
{
|
|
}
|
|
|
|
void
|
|
TLB::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
}
|
|
|
|
void
|
|
DTB::serialize(std::ostream &os)
|
|
{
|
|
TLB::serialize(os);
|
|
}
|
|
|
|
void
|
|
DTB::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
TLB::unserialize(cp, section);
|
|
}
|
|
|
|
/* end namespace X86ISA */ }
|
|
|
|
X86ISA::ITB *
|
|
X86ITBParams::create()
|
|
{
|
|
return new X86ISA::ITB(this);
|
|
}
|
|
|
|
X86ISA::DTB *
|
|
X86DTBParams::create()
|
|
{
|
|
return new X86ISA::DTB(this);
|
|
}
|