into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/packet.hh:
Hand merge code
--HG--
extra : convert_revision : d659418f24f4f4bf9867fec8573a5d227c0dfcea
src/mem/cache/base_cache.cc:
Fix a bug about not having a request to send
src/mem/cache/base_cache.hh:
Fix a bug with the blocking code
src/mem/cache/cache.hh:
AFix a bug with snoop hits in WB buffer
src/mem/cache/cache_impl.hh:
Fix a bug with snoop hits in WB buffer
Also, add better DPRINTF's
src/mem/cache/miss/miss_queue.cc:
Fix a bug with upgrades (Need to clean it up later)
src/mem/cache/miss/mshr.cc:
Fix a memory leak bug, still some outstanding with writebacks not being deleted
src/mem/cache/miss/mshr_queue.cc:
Fix a bug about upgrades (need to clean up later)
src/mem/packet.hh:
Fix for newly added cmd attribute for upgrades
tests/configs/memtest.py:
More interesting testcase
--HG--
extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688
src/mem/bus.cc:
Put back the check to see if the bus is busy. Also, populate the fields in the packet to indicate when the first word and the entire packet will be delivered.
src/mem/bus.hh:
Remove the occupyBus function.
src/mem/packet.hh:
Added fields to the packet to indicate when the first chunk of a packet arrives, and when the entire packet arrives.
--HG--
extra : convert_revision : cfc7670a33913d48a04d02c6d2448290a51f2d3c
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
Hand merge.
--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
src/cpu/o3/cpu.cc:
Comment out reseting CPU structures for now. This can be updated to work in the future.
--HG--
extra : convert_revision : bc1a86e2fe47da5acb14ba8b64568b0355431f1c
Not fully implemented yet, but good enough for single level cache coherence
src/mem/packet.hh:
Add a bit to distinguish invalidates and upgrades
--HG--
extra : convert_revision : 5bf50d535857cea37fbdaf7993915d1332cb757e
Remove some dead code.
src/mem/cache/cache_impl.hh:
Upgrades don't need a response.
Moved satisfied check into bus so removed some dead code.
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/packet.hh:
Upgrades don't require a response
--HG--
extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
src/cpu/memtest/memtest.cc:
Fix functional return path
src/cpu/memtest/memtest.hh:
Add snoop ranges in
src/mem/cache/base_cache.cc:
Properly signal NACKED
src/mem/cache/cache_impl.hh:
Catch nacked packet and panic for now
--HG--
extra : convert_revision : 59a64e82254dfa206681c5f987e6939167754d67
src/mem/bus.cc:
Fixes to the previous hand merging, and put the snooping back into recvTiming and out of it's own function.
src/mem/bus.hh:
Put snooping back into recvTiming and not in it's own function.
--HG--
extra : convert_revision : fd031b7e6051a5be07ed6926454fde73b1739dc6
src/mem/physical.cc:
Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
Make memtester have a way to connect functionally
tests/configs/memtest.py:
Properly create 8 memtesters and connect them to the memory system
--HG--
extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
src/mem/cache/cache_impl.hh:
Add more usefull DPRINTF's
REmove the PC to get rid of asserts
--HG--
extra : convert_revision : 3f6d832b138d058dbe79bb5f42bd2db9c50b35b5
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.hh:
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct
--HG--
extra : convert_revision : 2e8e812bf7fd3ba2b4cba7f7173cb41862f761af
src/cpu/checker/thread_context.hh:
Checker's TC should only copy state, and not fully take over from the old context (prevents it from accidentally stealing the quiesce event).
--HG--
extra : convert_revision : 5760f9c5bae749f8d1df35e4c898df13e41b0224
src/cpu/SConscript:
Add memtester to the compilation environment.
Someone who knows this better should make the MemTest a cpu model parameter.
For now attached with the build of o3 cpu.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Update Memtest for new mem system
src/python/m5/objects/MemTest.py:
Update memtest python description
--HG--
extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482
so you can restore by a command line like this:
m5.opt fs.py --checkpoint_dir="/my/ckpt/dir" -c 3
configs/example/fs.py:
add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N.
--HG--
extra : convert_revision : bf9c8d3265a3875cdfb6a878005baa7ae29af90d
src/dev/ide_ctrl.cc:
this range change needs to be done for all pio devices, not just the ide.
src/dev/pcidev.cc:
range change needs to be done at here, not in the ide_ctrl file.
--HG--
extra : convert_revision : 60c65c55e965b02d671dba7aa8793e5a81f40348
src/cpu/simple/atomic.cc:
add in serialization of AtomicSimpleCPU _status. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.
--HG--
extra : convert_revision : 7000f660aecea6fef712bf81853d9a7b90d625ee
