Commit graph

5928 commits

Author SHA1 Message Date
Andreas Hansson
3b90f52b61 util: Add ini string as tooltip info in dot output
This patch adds the config ini string as a tooltip that can be
displayed in most browsers rendering the resulting svg. Certain
characters are modified for HTML output.

Tested on chrome and firefox.
2013-09-04 13:23:00 -04:00
Andreas Hansson
fad36b35c6 util: Add colours to the dot output
This patch is adding a splash of colour to the dot output to make it
easier to distinguish objects of different types. As a bonus, the
pastel-colour palette also makes the output look like a something from
the 21st century.
2013-09-04 13:22:59 -04:00
Andreas Hansson
62cf785178 util: Add class name to dot graph and output to svg
This patch adds the class name to the label, creates some more space
by increasing the rank separation, and additionally outputs the graph
as an editable SVG in addition to the PDF.
2013-09-04 13:22:58 -04:00
Andreas Hansson
19a5b68db7 arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.

The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.

--HG--
rename : build_opts/NOISA => build_opts/NULL
rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts
rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh
rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
2013-09-04 13:22:57 -04:00
Andreas Hansson
ea40297018 cpu: Move the branch predictor out of the BaseCPU
The branch predictor is guarded by having either the in-order or
out-of-order CPU as one of the available CPU models and therefore
should not be used in the BaseCPU. This patch moves the parameter to
the relevant CPU classes.
2013-09-04 13:22:56 -04:00
Andreas Hansson
bb1d2f3957 arch: Header clean up for NOISA resurrection
This patch is a first step to getting NOISA working again. A number of
redundant includes make life more difficult than it has to be and this
patch simply removes them. There are also some redundant forward
declarations removed.
2013-09-04 13:22:55 -04:00
Andreas Hansson
cead68a781 alpha: Move system virtProxy to Alpha only
This patch moves the system virtual port proxy to the Alpha system
only to make the resurrection of the NOISA slightly less
painful. Alpha is the only ISA that is actually using it.
2013-09-04 13:22:55 -04:00
Andreas Hansson
fdf6f6c4b6 scons: Enable build on OSX
This patch changes the SConscript to build gem5 with libc++ on OSX as
the conventional libstdc++ does not have the C++11 constructs that the
current code base makes use of (e.g. std::forward).

Since this was the last use of the transitional TR1, the unordered map
and set header can now be simplified as well.
2013-09-04 13:22:54 -04:00
Andreas Hansson
c6062a3981 cpu: Fix timing CPU isDrained comment formatting
This patch fixes up the comment formatting for isDrained in the timing
CPU.
2013-08-20 11:21:27 -04:00
Andreas Hansson
c57c452143 base: Fix VectorPrint initialisation
This patch changes how the initialisation of the VectorPrint struct is
done so that gcc 4.4 is happy again.
2013-08-20 11:21:26 -04:00
Andreas Hansson
b63631536d stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.
2013-08-19 03:52:36 -04:00
Lena Olson
646c4a23ca cpu: Accurately count idle cycles for simple cpu
Added a couple missing updates to the notIdleFraction stat. Without
these, it sometimes gives a (not) idle fraction that is greater than 1
or less than 0.
2013-08-19 03:52:35 -04:00
Andreas Hansson
c26911013c config: Command line support for multi-channel memory
This patch adds support for specifying multi-channel memory
configurations on the command line, e.g. 'se/fs.py
--mem-type=ddr3_1600_x64 --mem-channels=4'. To enable this, it
enhances the functionality of MemConfig and moves the existing
makeMultiChannel class method from SimpleDRAM to the support scripts.

The se/fs.py example scripts are updated to make use of the new
feature.
2013-08-19 03:52:34 -04:00
Andreas Hansson
49d88f08b0 mem: Change AbstractMemory defaults to match the common case
This patch changes the default parameter value of conf_table_reported
to match the common case. It also simplifies the regression and config
scripts to reflect this change.
2013-08-19 03:52:33 -04:00
Sascha Bischoff
e553844efc cpu: Fix TrafficGen trace playback
This patch addresses an issue with trace playback in the TrafficGen
where the trace was reset but the header was not read from the trace
when a captured trace was played back for a second time. This resulted
in parsing errors as the expected message was not found in the trace
file.

The header check is moved to an init funtion which is called by the
constructor and when the trace is reset. This ensures that the trace
header is read each time when the trace is replayed.

This patch also addresses a small formatting issue in a panic.
2013-08-19 03:52:32 -04:00
Andreas Hansson
6279eaf1f7 mem: Use STL deque in favour of list for DRAM queues
This patch changes the data structure used for the DRAM read, write
and response queues from an STL list to deque. This optimisation is
based on the observation that the size is small (and fixed), and that
the structures are frequently iterated over in a linear fashion.
2013-08-19 03:52:32 -04:00
Andreas Hansson
ac42db8134 mem: Perform write merging in the DRAM write queue
This patch implements basic write merging in the DRAM to avoid
redundant bursts. When a new access is added to the queue it is
compared against the existing entries, and if it is either
intersecting or immediately succeeding/preceeding an existing item it
is merged.

There is currently no attempt made at avoiding iterating over the
existing items in determining whether merging is possible or not.
2013-08-19 03:52:31 -04:00
Amin Farmahini
243f135e5f mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAM
This patch gets rid of bytesPerCacheLine parameter and makes the DRAM
configuration separate from cache line size. Instead of
bytesPerCacheLine, we define a parameter for the DRAM called
burst_length. The burst_length parameter shows the length of a DRAM
device burst in bits. Also, lines_per_rowbuffer is replaced with
device_rowbuffer_size to improve code portablity.

This patch adds a burst length in beats for each memory type, an
interface width for each memory type, and the memory controller model
is extended to reason about "system" packets vs "dram" packets and
assemble the responses properly. It means that system packets larger
than a full burst are split into multiple dram packets.
2013-08-19 03:52:30 -04:00
Andreas Hansson
7a61f667f0 cpu: Fix timing CPU drain check
This patch modifies the SimpleTimingCPU drain check to also consider
the fetch event. Previously, there was an assumption that there is
never a fetch event scheduled if the CPU is not executing
microcode. However, when a context is activated, a fetch even is
scheduled, and microPC() is zero.
2013-08-19 03:52:30 -04:00
Andreas Hansson
f7d44590cb alpha: Check interrupts before quiesce
This patch adds a check to the quiesce operation to ensure that the
CPU does not suspend itself when there are unmasked interrupts
pending. Without this patch there are corner cases when the CPU gets
an interrupt before the quiesce is executed and then never wakes up
again.
2013-08-19 03:52:29 -04:00
Sascha Bischoff
6211c24a96 stats: Fix issue when printing 2D vectors
This patch addresses an issue with the text-based stats output which
resulted in Vector2D stats being printed without subnames in the event
that one of the dimensions was of length 1.

This patch also fixes the total printing for the 2D vector. Previously
totals were printed without explicitly stating that a total was being
printed. This has been rectified in this patch.
2013-08-19 03:52:29 -04:00
Akash Bagdia
e7e17f92db power: Add voltage domains to the clock domains
This patch adds the notion of voltage domains, and groups clock
domains that operate under the same voltage (i.e. power supply) into
domains. Each clock domain is required to be associated with a voltage
domain, and the latter requires the voltage to be explicitly set.

A voltage domain is an independently controllable voltage supply being
provided to section of the design. Thus, if you wish to perform
dynamic voltage scaling on a CPU, its clock domain should be
associated with a separate voltage domain.

The current implementation of the voltage domain does not take into
consideration cases where there are derived voltage domains running at
ratio of native voltage domains, as with the case where there can be
on-chip buck/boost (charge pumps) voltage regulation logic.

The regression and configuration scripts are updated with a generic
voltage domain for the system, and one for the CPUs.
2013-08-19 03:52:28 -04:00
Andreas Hansson
d5593f3c75 mem: Warn instead of panic for tXAW violation
Until the performance bug is fixed, avoid killing simulations.
2013-08-19 03:52:26 -04:00
Andreas Hansson
7bc3eaec7a mem: Allow disabling of tXAW through a 0 activation limit
This patch fixes an issue where an activation limit of 0 was not
allowed. With this patch, setting the limit to 0 simply disables the
tXAW constraint.
2013-08-19 03:52:26 -04:00
Andreas Hansson
2a675aecb9 mem: Add an internal packet queue in SimpleMemory
This patch adds a packet queue in SimpleMemory to avoid using the
packet queue in the port (and thus have no involvement in the flow
control). The port queue was bound to 100 packets, and as the
SimpleMemory is modelling both a controller and an actual RAM, it
potentially has a large number of packets in flight. There is
currently no limit on the number of packets in the memory controller,
but this could easily be added in a follow-on patch.

As a result of the added internal storage, the functional access and
draining is updated. Some minor cleaning up and renaming has also been
done.

The memtest regression changes as a result of this patch and the stats
will be updated.
2013-08-19 03:52:25 -04:00
Andreas Hansson
9b2effd9e2 cpu: Fix a bug in the O3 CPU introduced by the cache line patch
This patch fixes a bug in the O3 fetch stage that was introduced when
the cache line size was moved to the system. By mistake, the
initialisation and resetting of the fetch stage was merged and put in
the constructor. The resetting is now re-added where it should be.
2013-08-19 03:52:24 -04:00
Nilay Vaish
95381f8a99 ruby: slicc: remove double trigger, continueProcessing
These constructs are not in use and are not being maintained by any one.
In addition, it is not known if doubleTrigger works correctly with Ruby now.
2013-08-07 14:51:18 -05:00
Nilay Vaish
f1b17bf157 ruby: slicc: move some code to AbstractController
Some of the code in StateMachine.py file is added to all the controllers and
is independent of the controller definition. This code is being moved to the
AbstractController class which is the parent class of all controllers.
2013-08-07 14:51:18 -05:00
Nilay Vaish
e038741598 x86: add tlb checkpointing
This patch adds checkpointing support to x86 tlb. It upgrades the
cpt_upgrader.py script so that previously created checkpoints can
be updated. It moves the checkpoint version to 6.
2013-08-07 14:51:17 -05:00
Andreas Sandberg
b5bb2a25aa cpu: Remove unused getBranchPred() method from BaseCPU
Remove unused virtual getBranchPred() method from BaseCPU as it is not
implemented by any of the CPU models. It used to always return NULL.
2013-07-19 11:52:07 +02:00
Andreas Hansson
d4273cc9a6 mem: Set the cache line size on a system level
This patch removes the notion of a peer block size and instead sets
the cache line size on the system level.

Previously the size was set per cache, and communicated through the
interconnect. There were plenty checks to ensure that everyone had the
same size specified, and these checks are now removed. Another benefit
that is not yet harnessed is that the cache line size is now known at
construction time, rather than after the port binding. Hence, the
block size can be locally stored and does not have to be queried every
time it is used.

A follow-on patch updates the configuration scripts accordingly.
2013-07-18 08:31:16 -04:00
Xiangyu Dong
4e8ecd7c6f mem: Add cache class destructor to avoid memory leaks
Make valgrind a little bit happier
2013-07-18 08:29:47 -04:00
Andreas Hansson
204df3b928 sim: Make MaxTick in Python match the one in C++
This patch aligns the MaxTick in Python with the one in C++. Thus,
both reflect the maximum value that an unsigned 64-bit integer can
have.
2013-07-18 08:29:08 -04:00
Deyuan Guo
fb29dcf378 loader: Load weak symbols for function tracing 2013-07-15 18:08:57 -04:00
Umesh Bhaskar
5ba9e7afe2 debug : Fixes the issue wherein Debug symbols were not getting dumped into trace files for SE mode 2013-07-15 11:08:34 -04:00
Steve Reinhardt
1f43e244bd dev: make BasicPioDevice take size in constructor
Instead of relying on derived classes explicitly assigning
to the BasicPioDevice pioSize field, require them to pass
a size value in to the constructor.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-07-11 21:57:04 -05:00
Steve Reinhardt
502ad1e675 dev: consistently end device classes in 'Device'
PciDev and IntDev stuck out as the only device classes that
ended in 'Dev' rather than 'Device'.  This patch takes care
of that inconsistency.

Note that you may need to delete pre-existing files matching
build/*/python/m5/internal/param_* as scons does not pick up
indirect dependencies on imported python modules when generating
params, and the PciDev -> PciDevice rename takes place in a
file (dev/Device.py) that gets imported quite a bit.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-07-11 21:56:50 -05:00
Steve Reinhardt
2737650a69 dev/arm: get rid of AmbaDev namespace
It was confusing having an AmbaDev namespace along with an
AmbaDevice class.  The namespace stuff is now moved in to
a new base AmbaDevice class, which is a mixin for classes
AmbaPioDevice (the former AmbaDevice) and AmbaDmaDevice
to provide the readId function as an inherited member function.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-07-11 21:56:39 -05:00
Steve Reinhardt
b0b1c0205c devices: make more classes derive from BasicPioDevice
A couple of devices that have single fixed memory mapped regions
were not derived from BasicPioDevice, when that's exactly
the functionality that BasicPioDevice provides.  This patch
gets rid of a little bit of redundant code by making those
devices actually do so.

Also fixed the weird case of X86ISA::Interrupts, where
the class already did derive from BasicPioDevice but
didn't actually use all the features it could have.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-07-11 21:56:24 -05:00
Brad Beckmann
8e54c93222 ruby: removed the very old double trigger hack
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-07-11 13:56:05 -05:00
Nilay Vaish
1be0098c0b ruby: append transition comment only when in opt/debug 2013-06-28 21:42:27 -05:00
Nilay Vaish
b3980cdb9a ruby: network: remove reconfiguration code
This code seems not to be of any use now. There is no path in the simulator
that allows for reconfiguring the network. A better approach would be to
take a checkpoint and start the simulation from the checkpoint with the new
configuration.
2013-06-28 21:36:37 -05:00
Prakash Ramrakhyani
ac515d7a9b mem: Reorganize cache tags and make them a SimObject
This patch reorganizes the cache tags to allow more flexibility to
implement new replacement policies. The base tags class is now a
clocked object so that derived classes can use a clock if they need
one. Also having deriving from SimObject allows specialized Tag
classes to be swapped in/out in .py files.

The cache set is now templatized to allow it to contain customized
cache blocks with additional informaiton. This involved moving code to
the .hh file and removing cacheset.cc.

The statistics belonging to the cache tags are now including ".tags"
in their name. Hence, the stats need an update to reflect the change
in naming.
2013-06-27 05:49:50 -04:00
Andreas Hansson
0d68d36b9d mem: Remove the cache builder
This patch removes the redundant cache builder class.
2013-06-27 05:49:50 -04:00
Andreas Hansson
a0e551869c config: Remove Clock parameter multiplication
This patch removes the multiplication operator support for Clock
parameters as this functionality is now achieved by creating derived
clock domains.

Nate, this one is for you.
2013-06-27 05:49:50 -04:00
Akash Bagdia
7d7ab73862 sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.

The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).

The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.

All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.

The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 05:49:49 -04:00
Akash Bagdia
076d04a653 config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.

As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.

The configs and tests are updated accordingly.
2013-06-27 05:49:49 -04:00
Akash Bagdia
7eccb1b779 config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
2013-06-27 05:49:49 -04:00
Andreas Hansson
3b92748937 mem: Tidy up the bridge with const and additional checks
This patch does a bit of tidying up in the bridge code, adding const
where appropriate and also removing redundant checks and adding a few
new ones.

There are no changes to the behaviour of any regressions.
2013-06-27 05:49:49 -04:00
Andreas Hansson
f25ea3fd56 mem: Fix CommMonitor style and response check
This patch fixes the CommMonitor local variable names, and also
introduces a variable to capture if it expects to see a response. The
latter check considers both needsResponse and memInhibitAsserted.
2013-06-27 05:49:49 -04:00