gem5/src
Akash Bagdia 7eccb1b779 config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
2013-06-27 05:49:49 -04:00
..
arch x86: Add support for maintaining the x87 tag word 2013-06-18 16:36:08 +02:00
base base: Fix address range granularity calculation 2013-06-27 05:49:49 -04:00
cpu config: Remove redundant explicit setting of default clocks 2013-06-27 05:49:49 -04:00
dev config: Remove redundant explicit setting of default clocks 2013-06-27 05:49:49 -04:00
doc MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
mem config: Remove redundant explicit setting of default clocks 2013-06-27 05:49:49 -04:00
proto base: Avoid size limitation on protobuf coded streams 2013-05-30 12:53:53 -04:00
python base: Make the Python module loader PEP302 compliant 2013-06-03 13:51:03 +02:00
sim sim: Revert [34e3295b0e39] (sim: Fix early termination in mult...) 2013-06-11 09:24:10 +02:00
unittest AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript scons: don't die on warnings in swig-generated code 2013-03-27 10:03:02 -07:00