Commit graph

22 commits

Author SHA1 Message Date
Steve Reinhardt
8031cd93b5 Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
2005-06-01 21:44:00 -04:00
Nathan Binkert
5eab6c4b41 Make the notion of a global event tick independent of the actual
CPU cycle ticks.  This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency.  For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.

arch/alpha/ev5.cc:
    The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
    frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
    frequency isn't the cpu parameter anymore, cycleTime is.
    create several public functions for getting the cpu frequency
    and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
    Now that ticks aren't cpu cycles, fixup code to advance
    by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
    Provide a function to get the number of ticks for a given
    number of cycles.
dev/alpha_console.cc:
    Update for changes in the way that frequencies and latencies are
    accessed.  Move some stuff to init()
dev/alpha_console.hh:
    Need a pointer to the system and the cpu to get the frequency
    so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
    outline the constructor and destructor
dev/platform.hh:
    outline the constructor and destructor.
    don't keep track of the interrupt frequency.  Only provide the
    accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
    outline the constructor and destructor
    Don't set the interrupt frequency here.  Get it from the actual device
    that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
    Make the interrupt interval a configuration parameter.  (And convert
    the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
kern/tru64/tru64_system.cc:
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
python/m5/config.py:
    Fix support for cycle_time relative latencies and frequencies.
    Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
    All CPUs now have a cycle_time.  The default is the global frequency,
    but it is now possible to set the global frequency to some large value
    (like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
    Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
    We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
    Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
    this frequency isn't needed.  We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
    The clock generator should hold the frequency
sim/eventq.hh:
    Need to remove this assertion because the writeback event
    queue is different from the CPU's event queue which can cause
    this assertion to fail.
sim/process.cc:
    Fix comment.
sim/system.hh:
    Struct member to hold the boot CPU's frequency.
sim/universe.cc:
    remove unneeded variable.

--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 15:32:06 -04:00
Ron Dreslinski
9dd1ab1dba Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : db688679bfd9c670ef44611de71640c3bf564fc0
2005-02-21 16:50:38 -05:00
Nathan Binkert
9b1e2db811 Clean up CPU stuff and make it use params structs
cpu/base_cpu.cc:
cpu/base_cpu.hh:
    Convert the CPU stuff to use a params struct
cpu/memtest/memtest.cc:
    The memory tester is really not a cpu, so don't derive from
    BaseCPU since it just makes things a pain in the butt.  Keep
    track of max loads in the memtest class now that the base class
    doesn't do it for us.
    Don't have any default parameters.
cpu/memtest/memtest.hh:
    The memory tester is really not a cpu, so don't derive from
    BaseCPU since it just makes things a pain in the butt.  Keep
    track of max loads in the memtest class now that the base class
    doesn't do it for us.
cpu/simple_cpu/simple_cpu.cc:
    Convert to use a params struct.
    remove default parameters
cpu/simple_cpu/simple_cpu.hh:
    convert to use a params struct
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
    this isn't really a cpu.  don't derive from BaseCPU
objects/MemTest.mpy:
    we only need one max_loads parameter
sim/main.cc:
    Don't check for the number of CPUs since we may be doing something
    else going on.  If we don't have anything to simulate, the
    simulator will exit anyway.

--HG--
extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5
2005-02-19 11:46:41 -05:00
Ron Dreslinski
d9317dd348 Some more useful debugging info for kernel panic and die events
Increase the default number of CSHR's, we should really fix this or make it a parameter

Use a setBlocked call to tell the bus it should block

New technique for sampling and switchover:
1) Sampler switchover event happens
2) All cpus in the current phase of sampling associated with this sampler are signaled to switchover
3) Each cpu drains it's pipe of things being executed (stops fetching and waits for empty pipe)
4) Once the pipe is empty the cpu calls back to the sampler to signal it has finished, and moves into the switchedout state (continues not to fetch)
5) The sampler collects all the signals, once all cpus are drained it calls the new cpu's in the next phase to takeover from the correct cpu
6) The statistics are reset and the next switchover time is calculated from this point

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    Reconfigure the way the sampling switchover works
cpu/pc_event.cc:
    More debugging information on kernel panic's
kern/linux/linux_system.cc:
    More debug info for Kernel Die events
kern/linux/linux_system.hh:
    More debug info for kernel die events

--HG--
extra : convert_revision : 61cc42e43ba738705aa1f1d167b65d4d6dee51ae
2005-02-09 10:27:00 -05:00
Steve Reinhardt
c9b0204e28 Add simple function-tracing support. Prints a message
every time the committed PC changes from one symbol scope
to another.
Set function_trace=y on target CPU to enable.
To defer start, use function_trace_start=<tick>
(in addition to setting function_trace=y).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
    Add simple function-tracing support.
cpu/simple_cpu/simple_cpu.cc:
    Add function_trace, function_trace_start params
    Call traceFunctions() on instruction completion
cpu/simple_cpu/simple_cpu.hh:
    Add function_trace, function_trace_start params

--HG--
extra : convert_revision : 8a7f84028ccbaee585253629007f32fc8eae35e1
2004-11-16 17:20:38 -05:00
Nathan Binkert
4328480b56 Don't use the global check_interrupts variable. Add a per-cpu
checkInterrupts variable and use that to determine whether an interrupt
can occur on a given cycle.

arch/alpha/ev5.cc:
    XC -> CPU (and xc -> CPU) since we're really talking about a CPU here
    Don't use the global check_interrupts variable.  Add a per-cpu
    checkInterrupts variable and use that to determine whether an interrupt
    can occur on a given cycle.

--HG--
extra : convert_revision : be4c0247e5834005c60a45796a222cffd327b64e
2004-11-10 18:37:19 -05:00
Nathan Binkert
d82e0d11d1 make activation of exec contexts happen in startup
the registration stuff all moves into BaseCPU

cpu/base_cpu.cc:
    Move the registration stuff into the BaseCPU since all
    other CPUs use it.
cpu/base_cpu.hh:
    Move the defer registration stuff into the BaseCPU since all
    other CPUs use it.
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    registration stuff moved to base class
sim/system.cc:
    the activation of exec contexts should happen at startup, not
    when they are registered.
sim/system.hh:
    the system now has a startup function

--HG--
extra : convert_revision : bb6a7c2da5a1ecf5fe7ede1078200bfe5245f8ef
2004-11-03 20:46:33 -05:00
Ali Saidi
074969f8f1 Serialized cpu interrupts
cpu/simple_cpu/simple_cpu.cc:
    called basecpu serialization

--HG--
extra : convert_revision : 1a639b5e3c08e47a5d581c18b2b53fe87bd05b73
2004-06-17 15:36:59 -04:00
Ali Saidi
2f316082e4 Updated Copyright with information in bitkeeper changelogs
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/full_cpu/op_class.hh:
cpu/full_cpu/smt.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/platform.cc:
dev/platform.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.hh:
dev/tsunamireg.h:
docs/stl.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/m5/m5.c:
util/m5/m5op.h:
util/tap/tap.cc:
    Updated Copyright
dev/console.cc:
dev/console.hh:
    This code isn't ours, and shouldn't have our copyright

--HG--
extra : convert_revision : 598f2e5eab5d5d3de2c1e862b389086e3212f7c4
2004-06-08 13:37:27 -04:00
Nathan Binkert
62d756f253 rename namespace Statistics to Stats
--HG--
extra : convert_revision : 28f1703f8d7d8cf33fb952ae450f66bdba860fb7
2004-05-21 13:39:20 -04:00
Lisa Hsu
a0ccdf8aba merge m5 with linux for the event and binning lifting
--HG--
extra : convert_revision : 09d3678746c2e9a93a9982dc75d5e1ac309cb2fa
2004-05-18 01:40:03 -04:00
Nathan Binkert
a4d7bb113a Make a new stat type of Value which is a scalar stat that
proxies for a real C/C++ scalar value or scalar functor.
This replaces the scalar() and functor() terms that were
previously used in formulas.  This helps when dumping
statistics because the formulas are not supposed to change.

cpu/base_cpu.cc:
    Add a number of cycles stat to the cpu object that tracks the
    number of cycles that the cpu has executed.  This starts to pave
    the way for cpu cycles being different from event ticks.
cpu/base_cpu.hh:
    provide a functor for calculating all simulated instructions
    of all CPUs and a virtual function for determining that number.
    To deal with the change from functor() to Value::functor()
cpu/simple_cpu/simple_cpu.cc:
    simTicks -> numCycles
    numInsts is now a real Scalar stat, not a Formula
cpu/simple_cpu/simple_cpu.hh:
    numInsts is now a real Scalar stat, not a Formula
    count all instructions
sim/stat_control.cc:
    simInsts, simTicks, hostMemory, and hostSeconds are no
    longer Statistics::Formula but rather Statistics::Value
    add new stat for tick frequency
sim/stats.hh:
    don't need everything to be extern.
test/Makefile:
    Make stuff work a tad bit better
test/stattest.cc:
    test out Statistics::Value

--HG--
extra : convert_revision : c812e8baa2b17c08abf3a68ed1e1125dc6f2cfb4
2004-05-12 15:49:01 -04:00
Ali Saidi
b82bd8fd78 changed interrupt index to be 64 bits long and fixed a bad include
in adaptec_ctrl.hh

cpu/base_cpu.cc:
    changed index to 64bits
cpu/base_cpu.hh:
    changed index to 64 bits

--HG--
extra : convert_revision : e70d5f09f6066b90fca82cae22bb7d7eb705d65e
2004-02-16 00:21:42 -05:00
Steve Reinhardt
b79f6b3273 insn->inst
--HG--
extra : convert_revision : fcc556fb7e65855ec3c04ef272177c8e7a38fff9
2004-02-02 18:14:11 -08:00
Steve Reinhardt
4ce6118fda Factor ExecContext::setStatus(), BaseCPU::execCtxStatusChange(),
and SimpleCPU::setStatus() into separate functions.  For example,
setStatus(Active) is now activate().

--HG--
extra : convert_revision : 4392e07caf6c918db0b535f613175109681686fe
2003-12-10 17:47:28 -08:00
Steve Reinhardt
91cb532f9f Make FullCPU schedule its TickEvent when one of its contexts becomes active.
This fixes detailed-mpboot, which was broken as of my last change.
Also clean up some of the ExecContext status initialization.

cpu/base_cpu.hh:
    CPU::execCtxStatusChg() now takes thread_num as an arg so the CPU knows
    which execContext had the status change.
    BaseCPU::registerExecContexts() no longer needs to be virtual.
cpu/exec_context.cc:
    Initialize _status directly... don't use setStatus() as this will notify the CPU
    of the change before it is ready.
    CPU::execCtxStatusChg() now takes thread_num as an arg so the CPU knows
    which execContext had the status change.
cpu/exec_context.hh:
    Don't need initStatus() any more.
cpu/simple_cpu/simple_cpu.cc:
    Move execCtxStatusChg() from header to .cc file.
    No longer need specialized version of registerExecContexts to schedule TickEvent.
cpu/simple_cpu/simple_cpu.hh:
    Move execCtxStatusChg() from header to .cc file.
    CPU::execCtxStatusChg() now takes thread_num as arg (must be 0 for SimpleCPU).
    No longer need specialized version of registerExecContexts to schedule TickEvent.
kern/tru64/tru64_system.cc:
    Don't need initRegs; the PC etc. get initialized in the CPU constructor.
    ExecContexts start out as Unallocated, so no need to set them to Unallocated here.
kern/tru64/tru64_system.hh:
    Don't need initRegs; the PC etc. get initialized in the CPU constructor.
sim/prog.cc:
    ExecContexts start out as Unallocated, so no need to set them to Unallocated here.

--HG--
extra : convert_revision : e960ebbeb845960344633798e251b6c8bf1c0378
2003-10-24 23:02:36 -07:00
Steve Reinhardt
f5da73b688 Initial support for CPU switching. New SamplingCPU object encompasses a set
of CPUs that get switched round-robin (though currently we're only shooting for
two CPUs and one switch event, and even that doesn't quite work yet).  Registration
of ExecContexts with System/Process object factored out so we can create two CPUs
but only register one of them at a time.  Also worked at making behavior and naming
in System and Process objects more consistent.

arch/alpha/ev5.cc:
    Rename ipr_init to initIPRs and get rid of unused mem arg.
arch/alpha/fake_syscall.cc:
    Process:numCpus is now a function (not a data member).
base/remote_gdb.hh:
    Support for ExecContext switching.
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
    Support for ExecContext switching.
    Renamed contexts array to execContexts to be consistent with Process.
    CPU ID now auto-assigned by system object.
cpu/simple_cpu/simple_cpu.cc:
    Support for ExecContext switching.
    Renamed contexts array to execContexts to be consistent with Process.
    CPU ID now auto-assigned by system object.
    Cleaned up MP full-system initialization a bit.
dev/alpha_console.cc:
    Renamed xcvec array to execContexts to be consistent with Process.
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
    Support for ExecContext switching.
    CPU ID now auto-assigned by system object.
sim/prog.cc:
sim/prog.hh:
    Support for ExecContext switching.
    Process:numCpus is now a function (not a data member).
sim/system.cc:
sim/system.hh:
    Support for ExecContext switching.
    Renamed xcvec array to execContexts to be consistent with Process.

--HG--
extra : convert_revision : 79649cffad5bf3e83de8df44236941907926d791
2003-10-23 19:07:52 -07:00
Steve Reinhardt
f951b00d89 Get rid of obsolete code, most of it '#if 0'ed anyway.
Mostly vestiges of Dave's long-gone instruction prefetching stuff.

arch/alpha/isa_traits.hh:
    Delete unused extractInstructionPrefetchTarget().
base/inifile.cc:
    Delete '#if 0' code
cpu/base_cpu.hh:
    Delete unused filterThisInstructionPrefetch() function.
cpu/exetrace.hh:
    Delete '#if 0' code (obsolete flags).

--HG--
extra : convert_revision : c8317f56ba0a0e568daa785825ee938584987bed
2003-10-19 17:30:26 -07:00
Erik Hallnor
4134477369 Add a commited loads event queue similar to the one for commited instructions.
Two new parameters for the CPU models, max_loads_any_thread and max_loads_all_threads.

cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
    Swap out maxReads for the new commited loads model.

--HG--
extra : convert_revision : 35031329bbc476122b2203104537a9f8b46addfa
2003-10-16 17:04:18 -04:00
Steve Reinhardt
25693e9e69 Make include paths explicit and update makefile accordingly.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/faults.cc:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/circlebuf.cc:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/cprintf.cc:
base/cprintf.hh:
base/fast_alloc.cc:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/exec_aout.h:
base/loader/exec_ecoff.h:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/misc.cc:
base/misc.hh:
base/pollevent.cc:
base/pollevent.hh:
base/random.cc:
base/random.hh:
base/range.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/trace.cc:
base/trace.hh:
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
sim/debug.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/prog.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/sim_time.cc:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/tap/tap.cc:
    Make include paths explicit.

--HG--
extra : convert_revision : 941cbdc591fd4d3d1d9f095cd58fc23dd2d73840
2003-10-10 11:09:00 -07:00
Steve Reinhardt
52b31ea0a6 File moves for the reorg. Tree is in broken state until I commit the makefile and
#include changes.

--HG--
rename : sim/cache/lzss_compression.cc => base/compression/lzss_compression.cc
rename : sim/cache/lzss_compression.hh => base/compression/lzss_compression.hh
rename : sim/cache/null_compression.hh => base/compression/null_compression.hh
rename : sim/hybrid_pred.cc => base/hybrid_pred.cc
rename : sim/hybrid_pred.hh => base/hybrid_pred.hh
rename : base/aout_object.cc => base/loader/aout_object.cc
rename : base/aout_object.hh => base/loader/aout_object.hh
rename : base/coff_sym.h => base/loader/coff_sym.h
rename : base/coff_symconst.h => base/loader/coff_symconst.h
rename : base/ecoff_object.cc => base/loader/ecoff_object.cc
rename : base/ecoff_object.hh => base/loader/ecoff_object.hh
rename : base/elf_object.cc => base/loader/elf_object.cc
rename : base/elf_object.hh => base/loader/elf_object.hh
rename : base/exec_aout.h => base/loader/exec_aout.h
rename : base/exec_ecoff.h => base/loader/exec_ecoff.h
rename : base/object_file.cc => base/loader/object_file.cc
rename : base/object_file.hh => base/loader/object_file.hh
rename : base/symtab.cc => base/loader/symtab.cc
rename : base/symtab.hh => base/loader/symtab.hh
rename : sim/predictor.hh => base/predictor.hh
rename : sim/sat_counter.cc => base/sat_counter.cc
rename : sim/sat_counter.hh => base/sat_counter.hh
rename : sim/base_cpu.cc => cpu/base_cpu.cc
rename : sim/base_cpu.hh => cpu/base_cpu.hh
rename : sim/exec_context.cc => cpu/exec_context.cc
rename : sim/exec_context.hh => cpu/exec_context.hh
rename : sim/exetrace.cc => cpu/exetrace.cc
rename : sim/exetrace.hh => cpu/exetrace.hh
rename : sim/op_class.hh => cpu/full_cpu/op_class.hh
rename : sim/smt.hh => cpu/full_cpu/smt.hh
rename : sim/inst_seq.hh => cpu/inst_seq.hh
rename : sim/intr_control.cc => cpu/intr_control.cc
rename : sim/intr_control.hh => cpu/intr_control.hh
rename : sim/memtest.cc => cpu/memtest/memtest.cc
rename : sim/memtest.hh => cpu/memtest/memtest.hh
rename : sim/pc_event.cc => cpu/pc_event.cc
rename : sim/pc_event.hh => cpu/pc_event.hh
rename : sim/simple_cpu.cc => cpu/simple_cpu/simple_cpu.cc
rename : sim/simple_cpu.hh => cpu/simple_cpu/simple_cpu.hh
rename : sim/static_inst.cc => cpu/static_inst.cc
rename : sim/static_inst.hh => cpu/static_inst.hh
extra : convert_revision : 05bd41acb2a424f1a38609fd4ac6df681bb479d6
2003-10-10 09:57:26 -07:00
Renamed from sim/base_cpu.hh (Browse further)