4134477369
Two new parameters for the CPU models, max_loads_any_thread and max_loads_all_threads.
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
Swap out maxReads for the new commited loads model.
--HG--
extra : convert_revision : 35031329bbc476122b2203104537a9f8b46addfa
139 lines
4.3 KiB
C++
139 lines
4.3 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __BASE_CPU_HH__
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#define __BASE_CPU_HH__
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#include <vector>
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#include "sim/eventq.hh"
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#include "sim/sim_object.hh"
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#include "targetarch/isa_traits.hh" // for Addr
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#ifdef FULL_SYSTEM
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class System;
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#endif
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class BranchPred;
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class ExecContext;
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class BaseCPU : public SimObject
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{
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#ifdef FULL_SYSTEM
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protected:
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int number;
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Tick frequency;
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uint8_t interrupts[NumInterruptLevels];
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uint64_t intstatus;
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public:
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virtual void post_interrupt(int int_num, int index);
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virtual void clear_interrupt(int int_num, int index);
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virtual void clear_interrupts();
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bool check_interrupt(int int_num) const {
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if (int_num > NumInterruptLevels)
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panic("int_num out of bounds\n");
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return interrupts[int_num] != 0;
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}
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bool check_interrupts() const { return intstatus != 0; }
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uint64_t intr_status() const { return intstatus; }
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Tick getFreq() const { return frequency; }
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#endif
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protected:
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std::vector<ExecContext *> contexts;
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public:
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virtual void execCtxStatusChg() {}
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public:
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#ifdef FULL_SYSTEM
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BaseCPU(const std::string &_name, int _number_of_threads,
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Counter max_insts_any_thread, Counter max_insts_all_threads,
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Counter max_loads_any_thread, Counter max_loads_all_threads,
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System *_system,
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int num, Tick freq);
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#else
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BaseCPU(const std::string &_name, int _number_of_threads,
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Counter max_insts_any_thread = 0,
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Counter max_insts_all_threads = 0,
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Counter max_loads_any_thread = 0,
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Counter max_loads_all_threads = 0);
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#endif
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virtual ~BaseCPU() {}
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virtual void regStats();
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/**
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* Number of threads we're actually simulating (<= SMT_MAX_THREADS).
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* This is a constant for the duration of the simulation.
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*/
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int number_of_threads;
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/**
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* Vector of per-thread instruction-based event queues. Used for
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* scheduling events based on number of instructions committed by
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* a particular thread.
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*/
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EventQueue **comInsnEventQueue;
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/**
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* Vector of per-thread load-based event queues. Used for
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* scheduling events based on number of loads committed by
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*a particular thread.
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*/
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EventQueue **comLoadEventQueue;
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#ifdef FULL_SYSTEM
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System *system;
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#endif
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virtual bool filterThisInstructionPrefetch(int thread_number,
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short asid, Addr prefetchTarget) const { return true; }
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/**
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* Return pointer to CPU's branch predictor (NULL if none).
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* @return Branch predictor pointer.
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*/
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virtual BranchPred *getBranchPred() { return NULL; };
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private:
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static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
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public:
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static int numSimulatedCPUs() { return cpuList.size(); }
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};
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#endif // __BASE_CPU_HH__
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