Brad Beckmann
c3204421d8
ruby: Ruby memtest python script.
2009-11-18 13:55:57 -08:00
Derek Hower
b3b8e309ed
Added tag Calvin_Submission for changeset 5de565c4b7bd
2009-11-18 11:55:42 -06:00
Derek Hower
9ef5e72917
ruby: added sequencer stats to track what requests are waiting on
2009-11-18 11:55:30 -06:00
Derek Hower
d11dd6ed2c
ruby: turned off randomization by default, turned on memory controller random arbitrate
2009-11-18 11:53:43 -06:00
Ali Saidi
422f0d9f10
ARM: Begin implementing CP15
2009-11-17 18:02:09 -06:00
Ali Saidi
0916c376a9
ARM: Differentiate between LDM exception return and LDM user regs.
2009-11-17 18:02:08 -06:00
Ali Saidi
1470dae8e9
ARM: Boilerplate full-system code.
...
--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
2009-11-17 18:02:08 -06:00
Ali Saidi
171e7f7b24
imported patch isa_fixes2.diff
2009-11-16 11:37:03 -06:00
Gabe Black
9127ee5ac8
ARM: Make the exception return form of ldm restore CPSR.
2009-11-15 00:23:14 -08:00
Gabe Black
903fb8c73d
ARM: Create a new type of load uop that restores spsr into cpsr.
2009-11-15 00:15:42 -08:00
Gabe Black
b41725f723
ARM: Check in the actual change from the last commit.
...
The last commit was somehow empty. This was what was supposed to go in it.
2009-11-14 21:03:10 -08:00
Gabe Black
5ca47da599
ARM: Switch the immediate and register versions of msr.
...
These were accidently transposed. This change straightens them out.
2009-11-14 20:57:59 -08:00
Gabe Black
c4042985d7
ARM: Fix up the implmentation of the msr instruction.
2009-11-14 19:22:30 -08:00
Gabe Black
e2ab64543b
ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.
2009-11-14 19:22:30 -08:00
Gabe Black
425ebf6bd7
ARM: Add a bitfield to indicate if an immediate should be used.
2009-11-14 19:22:30 -08:00
Gabe Black
e543f16247
ARM: Write some functions to write to the CPSR and SPSR for instructions.
2009-11-14 19:22:30 -08:00
Gabe Black
812e390693
ARM: Fix up the implmentation of the mrs instruction.
2009-11-14 19:22:29 -08:00
Gabe Black
1df0025e28
ARM: More accurately describe the effects of using the control operands.
2009-11-14 19:22:29 -08:00
Gabe Black
50b9149c75
ARM: Hook up the moded versions of the SPSR.
...
These registers can be accessed directly, or through MISCREG_SPSR which will
act as whichever SPSR is appropriate for the current mode.
2009-11-14 19:22:29 -08:00
Ali Saidi
4e9ce1805e
SE: Fix SE mode OS X compilation.
2009-11-14 11:49:01 -06:00
Ali Saidi
48bc573f5f
ARM: Move around decoder to properly decode CP15
2009-11-14 11:25:00 -06:00
Derek Hower
2f5839832e
ruby: added -A option to TwoLevel_SplitL1UnifiedL2 to set the L1 cache size
2009-11-13 09:45:23 -06:00
Derek Hower
f7f475a6f4
ruby: gave ALIASED_REQUEST priority over BUFFER_FULL in sequencer
2009-11-13 09:44:51 -06:00
Derek Hower
2ee04d6587
ruby: reduce the memory usage of ruby by making memory vector page based
2009-11-13 09:43:39 -06:00
Derek Hower
ceb8fde914
ruby: cache memory bugfix
2009-11-13 09:42:47 -06:00
Vince Weaver
8f6744c19c
X86: add ULL to 1's being shifted in 64-bit values
...
Some of the micro-ops weren't casting 1 to ULL before shifting,
which can cause problems. On the perl makerand input this
caused some values to be negative that shouldn't have been.
The casts are done as ULL(1) instead of 1ULL to match others
in the m5 code base.
2009-11-11 17:49:09 -05:00
Gabe Black
5524af83ef
ARM: Fix some bugs in the ISA desc and fill out some instructions.
2009-11-10 23:44:05 -08:00
Gabe Black
850eb54a7c
Merge with the head.
2009-11-10 21:12:53 -08:00
Gabe Black
b8120f6c38
Mem: Eliminate the NO_FAULT request flag.
2009-11-10 21:10:18 -08:00
Gabe Black
2e28da5583
ARM: Implement fault classes.
...
Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
2009-11-10 20:34:38 -08:00
Gabe Black
4779020e13
ARM: Fix the integer register indexes.
...
The PC indexes in the various register sets was defined in the section for
unaliased registers which was throwing off the indexing. This moves those
where they belong. Also, to make detecting accesses to the PC easier and
because it's in the same place in all modes, the intRegForceUser function
now passes it through as index 15.
2009-11-10 20:19:55 -08:00
Vince Weaver
53e27c0277
X86: Fix bugs in movd implementation.
...
Unfortunately my implementation of the movd instruction had two bugs.
In one case, when moving a 32-bit value into an xmm register, the
lower half of the xmm register was not zero extended.
The other case is that xmm was used instead of xmmlm as the source
for a register move. My test case didn't notice this at first
as it moved xmm0 to eax, which both have the same register
number.
2009-11-10 11:29:30 -05:00
Vince Weaver
e81cc233a6
X86: Remove double-cast in Cvtf2i micro-op
...
This double cast led to rounding errors which caused
some benchmarks to get the wrong values, most notably lucas
which failed spectacularly due to CVTTSD2SI returning an
off-by-one value. equake was also broken.
2009-11-10 11:18:23 -05:00
Vince Weaver
7da221ca82
syscall: missing initializer in getcwd call
...
This one case was missed during the update to stack-based arguments.
Without this fix, m5 will crash during a gwtcwd call, at least
with X86.
2009-11-09 10:02:55 -05:00
Gabe Black
bbbfdee2ed
X86: Don't panic on faults on prefetches in SE mode.
2009-11-08 22:49:58 -08:00
Gabe Black
44e912c6bd
X86: Explain what really didn't work with unmapped addresses in SE mode.
2009-11-08 22:49:57 -08:00
Gabe Black
53086dfefe
X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.
2009-11-08 22:49:57 -08:00
Nathan Binkert
b1a1f9aec8
automerge
2009-11-08 20:15:54 -08:00
Nathan Binkert
14b5169750
tests: update statistics for change caused by vsyscall support in x86
...
Caused by a slight change in memory layout.
2009-11-08 20:15:23 -08:00
Steve Reinhardt
374d337693
scons: deal with generated .py files properly
2009-11-08 17:35:49 -08:00
Gabe Black
8a4af3668d
ARM: Support forcing load/store multiple to use user registers.
2009-11-08 15:49:03 -08:00
Gabe Black
bb903b6514
ARM: Simplify the load/store multiple generation code.
...
Specifically, get rid of the big switch statement so more cases can be
handled. Enumerating all the possible settings doesn't scale well. Also do
some minor style clean up.
2009-11-08 15:16:59 -08:00
Nathan Binkert
708faa7677
compile: wrap 64bit numbers with ULL() so 32bit compiles work
...
In the isa_parser, we need to check case statements.
2009-11-08 13:31:59 -08:00
Gabe Black
48525f581c
ARM: Split the condition codes out of the CPSR.
...
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
2009-11-08 02:08:40 -08:00
Gabe Black
d188821d37
ARM: Add in more bits for the mon mode.
2009-11-08 02:01:02 -08:00
Gabe Black
3a3e846151
ARM: Get rid of NumInternalProcRegs.
...
That constant is a carry over from Alpha and doesn't do anything in ARM.
2009-11-08 02:00:55 -08:00
Gabe Black
78bd8fe44f
ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.
2009-11-08 01:59:20 -08:00
Gabe Black
f63c260d89
ARM: Get rid of the Raddr operand.
2009-11-08 01:57:34 -08:00
Gabe Black
43e9209c21
ARM: Initialize processes in user mode.
...
I accidentally left in a change to test using int registers in system mode.
This change reverts that.
2009-11-08 00:54:32 -08:00
Gabe Black
a2b76516c4
ARM: Implement the shadow registers using register flattening.
2009-11-08 00:07:49 -08:00
