Commit graph

178 commits

Author SHA1 Message Date
Ron Dreslinski
28e9641c2c Use fixPacket function everywhere.
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
    Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Use fix Packet function
src/mem/packet.cc:
    Fix an assert that was checking the wrong thing
src/mem/tport.cc:
    Properly detect if we need to do the access to the functional device

--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
2006-10-20 13:01:21 -04:00
Ron Dreslinski
780aa0a0eb Fix corner case on assertion.
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.

src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Fix corner case on assertion
tests/configs/memtest.py:
    Updated memtester with uncacheable addresses and functional accesses

--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
2006-10-19 21:26:46 -04:00
Ron Dreslinski
cc1feb9f6d Fix memtester to use functional access, fix cache to work functionally now that we could test it.
src/cpu/memtest/memtest.cc:
    Fix memtest to do functional accesses
src/mem/cache/cache_impl.hh:
    Fix cache to handle functional accesses properly based on memtester changes
    Still need to fix functional accesses in timing mode now that the memtester can test it.

--HG--
extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
2006-10-19 21:07:53 -04:00
Ron Dreslinski
210e73f2a2 Small changes:
?? doesn't compile in warn statements
Should have been false, where I had a true.

src/cpu/o3/lsq_impl.hh:
    Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
    Forgot to signal atomic mode in snoopProbe

--HG--
extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
2006-10-19 20:18:17 -04:00
Ron Dreslinski
e34e564f79 Fixes to get single level uni-coherence to work.
Now to try L2 caches in FS.

src/mem/cache/base_cache.hh:
    Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
    Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
    Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Properly forward invalidates in atomic/timing uni-coherence

--HG--
extra : convert_revision : f0f11315e8e7f32c19d92287f6f9c27b079c96f7
2006-10-19 20:02:57 -04:00
Ron Dreslinski
9cf063eb8e Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : c6611b32537918f5bf183788227ddf69a9a9a069
2006-10-19 19:00:43 -04:00
Ron Dreslinski
39d24f7241 Always get the functional access from the highest level of cache first.
src/mem/cache/cache_impl.hh:
    Get the read data from the highest level of cache on a functional access

--HG--
extra : convert_revision : 7437ac46fb40f3ea3b42197a1aa8aec62af60181
2006-10-19 19:00:27 -04:00
Steve Reinhardt
bba3dfb0d3 First cut at LL/SC support in caches (atomic mode only).
configs/example/fs.py:
    Add MOESI protocol to caches (uni coherence not quite working w/FS yet).

--HG--
extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
2006-10-19 00:33:33 -07:00
Lisa Hsu
15770fb7b4 need some initializations before doing the loop.
--HG--
extra : convert_revision : e5e8b16ae4f119c923d8c0d295aa9569d7a8fe5b
2006-10-18 18:01:33 -04:00
Ron Dreslinski
5bcdc74fe2 Fix WriteInvalidateResp
--HG--
extra : convert_revision : ac4281944202a9a2f166b305a1eaea507e484bcc
2006-10-18 16:38:02 -04:00
Ron Dreslinski
63c2a782d6 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
2006-10-18 13:34:52 -04:00
Steve Reinhardt
0e2561710b Break a lot of overly long lines.
Factor out some asserts that were on both
sides of an if/else.

--HG--
extra : convert_revision : 78f0c2d76a81a98216b2f281159c6b6ea0147731
2006-10-18 08:41:05 -07:00
Steve Reinhardt
caf123586f Get rid of doData() lines (were already commented out).
Reindent due to resulting changes in nesting.

--HG--
extra : convert_revision : 6be099d572efb618efb08fbc06d7e0e4b5b4cab2
2006-10-18 08:24:24 -07:00
Steve Reinhardt
6cd187e1f0 Get rid of obsolete in-cache copy support.
--HG--
extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25
2006-10-18 08:16:22 -07:00
Steve Reinhardt
f735399b39 Include packet_impl.hh (need this on my laptop,
but not on zizzer... g++ 4 thing maybe?)

--HG--
extra : convert_revision : 31c49f1c55fe9daf6365411bfb5bb7f6ccc8032d
2006-10-17 21:16:17 -07:00
Ali Saidi
e51b075a27 add code to serialize se structures. Lisa is working on the python side of things and will test
src/mem/page_table.cc:
src/mem/page_table.hh:
    add code to serialize/unserialize page table
src/sim/process.cc:
src/sim/process.hh:
    add code to serialize/unserialize process

--HG--
extra : convert_revision : ee9eb5e2c38c5d317a2f381972c552d455e0db9e
2006-10-17 19:38:36 -04:00
Ron Dreslinski
9c582c7e14 Fixes for uni-coherence in timing mode for FS.
Still a bug in atomic uni-coherence in FS.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
    Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
    Only deallocate once

--HG--
extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
2006-10-17 18:50:19 -04:00
Ron Dreslinski
4fff6d4603 Fixes to cache eliminating the assumption that the Packet is still valid after sending out a request.
Still need to rework upgrades into this system, but works for now.

src/mem/cache/base_cache.cc:
    Re order code to be more readable
src/mem/cache/base_cache.hh:
    Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
    Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
    Demorgans to make it easier to understand
src/mem/tport.cc:
    Delete writebacks

--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
2006-10-17 16:47:22 -04:00
Ron Dreslinski
6e8bfa4e63 Properly chack the pkt pointer on upgrades to insure no segfaults when writebacks delete the packet.
--HG--
extra : convert_revision : 72b1c6296a16319f4d16c62bc7038365654dbc40
2006-10-17 15:07:40 -04:00
Ron Dreslinski
288b98eb69 Fix it so that the cache does not assume to gave the packet it sent out via sendTiming.
Still need to fix upgrades to use this path

src/mem/cache/base_cache.cc:
    Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed
src/mem/cache/cache_impl.hh:
    Use copy of packet, because sendTiming may have changed the pkt
    Also, delete the copy when the time comes

--HG--
extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
2006-10-17 15:05:21 -04:00
Ron Dreslinski
685e588b45 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : c3650273684f3fbdcd2e14e95d09ee3c6de8d6b6
2006-10-17 14:05:23 -04:00
Steve Reinhardt
9202422d6e Get rid of unused CacheBlk << output operator.
--HG--
extra : convert_revision : d5c0aadc35edf5c9495afcd3375f1f64716ef845
2006-10-14 02:09:05 -04:00
Ron Dreslinski
1871495b8d Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : f62790e46a7e3eb88a6f8c7bfaa08526285248a3
2006-10-13 15:47:35 -04:00
Ron Dreslinski
a17afb1649 Fix for DMA's in FS caches.
Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)

Now both timing/atomic caches with MOESI in UP fail at same point.

src/dev/io_device.hh:
    DMA's should send WriteInvalidates
src/mem/bridge.cc:
    Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Fix CSHR's for flow control.
src/mem/packet.hh:
    Make a writeInvalidateResp, since the DMA expects responses to it's writes

--HG--
extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
2006-10-13 15:47:05 -04:00
Ali Saidi
3d2764acf3 replace functional code in tport with fixPacket().
fixPacket() should be used anywhere a functional packet and timing packet are found to have the same address.

--HG--
extra : convert_revision : 783ec438271b24ddb0ae742b4efd1ed7d6be93f3
2006-10-12 15:30:30 -04:00
Ron Dreslinski
eddbb6801f Fix CSHR retrys
--HG--
extra : convert_revision : caa7664f6c945396fa38ce62fbda018ebed4eaa6
2006-10-12 15:02:56 -04:00
Ali Saidi
4a96779350 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 0e184a0784100112db5841c587bd3dd638f8bdc0
2006-10-12 15:02:50 -04:00
Ali Saidi
0615d92d33 small bus updates for functional accesses
--HG--
extra : convert_revision : c7a6b199c74ed4b4ffab14bbffb51e72d75b7742
2006-10-12 15:02:25 -04:00
Ron Dreslinski
3aaa3456dc Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : fa5b2cfa79d87a0612b8116d407a8b2959d9095a
2006-10-12 14:31:31 -04:00
Ron Dreslinski
fe230ddb8f Remove bus and top level parameters from cache
src/mem/cache/base_cache.hh:
    Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
    Remove top level parameters from the cache

--HG--
extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
2006-10-12 14:21:25 -04:00
Ali Saidi
2c9d506f46 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

src/mem/packet.hh:
    hand merge

--HG--
extra : convert_revision : 3f77707360235dc98c6b12a0367ca64a401313df
2006-10-12 14:18:42 -04:00
Ali Saidi
3ba2ed6aef add a traceflag for functional accesses
implement fix packet and add the ability to print a packet to a ostream
remove tabs in packet.hh (Could people stop inserting them??!?!?!)
mark const functions in packet.hh as such

src/base/traceflags.py:
    add a traceflag for functional accesses
src/mem/packet.cc:
    implement fix packet and add the ability to print a packet to a ostream
src/mem/packet.hh:
    add the ability to print a packet to an ostream
    remove tabs in file
    mark const functions as such

--HG--
extra : convert_revision : 4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
2006-10-12 14:15:09 -04:00
Ron Dreslinski
f89b56b61a Check the response queue on functional accesses.
The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses?

src/mem/cache/base_cache.cc:
src/mem/tport.cc:
    Add in functional check of retry queued packets.

--HG--
extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
2006-10-12 13:59:03 -04:00
Ron Dreslinski
ba4c224c39 Fix problems with unCacheable addresses in timing-coherence
src/base/traceflags.py:
src/mem/physical.cc:
    Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
    Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
    Set the size properly on unCacheable accesses

--HG--
extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
2006-10-12 13:33:21 -04:00
Ron Dreslinski
388d484269 Make default ID unique (not broadcast)
Fix a segfault associated with DefaultId

src/mem/bus.cc:
    Handle a segfault in the bus when DefaultPort was being used
src/mem/bus.hh:
    Make the Default ID more unique (it overlapped with Broadcast ID)

--HG--
extra : convert_revision : 9182805c5cf4d9fe004e6c5be8547a8f41ed7bfe
2006-10-11 20:54:06 -04:00
Ron Dreslinski
14c8e8b227 Forgot to mark myself as on the retry list
--HG--
extra : convert_revision : c20170320a284a7bf143a929e4d3aa1475a8bfe0
2006-10-11 19:47:11 -04:00
Ron Dreslinski
3c7e0ec752 Fix bus in FS mode.
src/mem/bus.cc:
    Add debugging statement
src/mem/bus.hh:
    Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
    Rework timing port to retry properly

--HG--
extra : convert_revision : fbfb5e8b4a625e49c6cd764da1df46a4f336b1b2
2006-10-11 19:25:48 -04:00
Ron Dreslinski
567afbf6ce More cache fixes. Atomic coherence now works as well.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
    Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
    Debug output.
    Clean up memleak in atomic mode.
    Set hitLatency.
    Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
    Add command strings for new commands
src/python/m5/objects/MemTest.py:
    Add param to test atomic memory.

--HG--
extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
2006-10-11 18:28:33 -04:00
Ron Dreslinski
03c42ea590 Update for Atomic Coherece with Gabes bus
--HG--
extra : convert_revision : 6a23052056d1c61cba0a4c77f1030cee419c6fa3
2006-10-11 01:59:38 -04:00
Ron Dreslinski
4e35c5656f Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 70187b8f04d0f8424512f64bdade05bf1aca85a3
2006-10-11 01:02:18 -04:00
Ron Dreslinski
c2012601e9 Use bus response time paramteres
Fix bug with deadlocking

src/mem/cache/base_cache.cc:
    Make sure to not wait anymore

--HG--
extra : convert_revision : 5f7b44a1c475820b9862275a0d6113ec2991735d
2006-10-11 01:01:40 -04:00
Gabe Black
7767f5af73 Don't call recvRetry if the bus is busy anyway. This takes care of a corner case as well when dealing with grants that aren't used.
--HG--
extra : convert_revision : 38f7ef1b41477fb2a2438387ef3a81cccd3e7a8a
2006-10-11 00:54:47 -04:00
Ron Dreslinski
07dad71f6f Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : d2d19b27533f35c6570ee84c6c83b2919f27b97f
2006-10-11 00:31:40 -04:00
Gabe Black
a139e4394d Make the bus work if the other sides recvRetry doesn't call sendTiming for some reason.
--HG--
extra : convert_revision : e722ddb0354a5c021dc7c44a3e2f0a64e962442b
2006-10-11 00:26:21 -04:00
Ron Dreslinski
04f71f1226 When turning asserts into if's don't forget to invert.
src/mem/cache/base_cache.cc:
    When turning asserts into if's don't forget to invert.
    Must be too sleepy.

--HG--
extra : convert_revision : ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
2006-10-11 00:19:31 -04:00
Ron Dreslinski
23bbd14426 Writebacks can be pulled out from under the BusRequest when snoops of uprgades to owned blocks hit in the WB buffer
--HG--
extra : convert_revision : f0502836a79ce303150daa7e571badb0bce3a97a
2006-10-11 00:13:53 -04:00
Ron Dreslinski
c9102b08fa Only issue responses if we aren;t already blocked
--HG--
extra : convert_revision : 511c0bcd44b93d5499eefa8399f36ef8b6607311
2006-10-10 23:53:10 -04:00
Ron Dreslinski
ca694ca7b1 Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/bus.cc:
    SCCS merged

--HG--
extra : convert_revision : 18608114350c466a56ab499ae523b01fcb2f6ef2
2006-10-10 23:37:14 -04:00
Gabe Black
8353b1e21f Make the bus is occupied for none broadcast packets as well.
--HG--
extra : convert_revision : aef3c625172e92be8f29c4c57077fefee43046bb
2006-10-10 23:28:33 -04:00
Ron Dreslinski
477a3b0b61 Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/bus.cc:
    SCCS merged

--HG--
extra : convert_revision : eaae105025635c37af06cf72bb061ce82def9dc9
2006-10-10 22:52:52 -04:00