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gem5/src/mem
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Ron Dreslinski 780aa0a0eb Fix corner case on assertion. 
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.

src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Fix corner case on assertion
tests/configs/memtest.py:
    Updated memtester with uncacheable addresses and functional accesses

--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
2006-10-19 21:26:46 -04:00
..
cache Fix corner case on assertion. 2006-10-19 21:26:46 -04:00
config Backing in more changsets, getting closer to compile 2006-06-28 14:35:00 -04:00
bridge.cc Fix for DMA's in FS caches. 2006-10-13 15:47:05 -04:00
bridge.hh Fix up doxygen. 2006-08-14 19:25:07 -04:00
bus.cc small bus updates for functional accesses 2006-10-12 15:02:25 -04:00
bus.hh Make default ID unique (not broadcast) 2006-10-11 20:54:06 -04:00
dram.cc Fix Physical Memory to allow memory sizes bigger than 128MB. 2006-08-16 19:01:11 -04:00
dram.hh Fix Physical Memory to allow memory sizes bigger than 128MB. 2006-08-16 19:01:11 -04:00
mem_object.cc Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
mem_object.hh Fix up doxygen. 2006-08-14 19:25:07 -04:00
packet.cc Fix WriteInvalidateResp 2006-10-18 16:38:02 -04:00
packet.hh Fix WriteInvalidateResp 2006-10-18 16:38:02 -04:00
page_table.cc need some initializations before doing the loop. 2006-10-18 18:01:33 -04:00
page_table.hh add code to serialize se structures. Lisa is working on the python side of things and will test 2006-10-17 19:38:36 -04:00
physical.cc Fix problems with unCacheable addresses in timing-coherence 2006-10-12 13:33:21 -04:00
physical.hh Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) 2006-10-08 10:53:24 -07:00
port.cc Fix up doxygen. 2006-08-14 19:25:07 -04:00
port.hh Move away from using the statusChange function on snoops. Clean up snooping code in general. 2006-10-08 18:48:03 -04:00
port_impl.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
request.hh Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) 2006-10-08 10:53:24 -07:00
tport.cc Fixes to cache eliminating the assumption that the Packet is still valid after sending out a request. 2006-10-17 16:47:22 -04:00
tport.hh Move more common functionality into SimpleTimingPort, 2006-08-30 16:24:26 -07:00
translating_port.cc Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
translating_port.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
vport.cc Fix up doxygen. 2006-08-14 19:25:07 -04:00
vport.hh Fix up doxygen. 2006-08-14 19:25:07 -04:00