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8549 commits

Author SHA1 Message Date
Ali Saidi
0c29a97ba9 Prefetch: Don't prefetch if address is in the write queue.
Check that we're not currently writing back an address the prefetcher is trying
to prefetch before issuing it. We previously checked the mshrQueue and the cache
itself, but forgot to check the writeBuffer. This fixes a memory corrucption
issue with an L2 prefetcher.
2011-09-13 12:06:13 -05:00
Prakash Ramrakhyani
e4830ad2eb gem5ops: Implement Java JNI for gem5Ops
These ops allow gem5 ops to be called from within java programs like the following:
import jni.gem5Op;

public  class HelloWorld {

    public static void main(String[] args) {
        gem5Op gem5 = new gem5Op();
        System.out.println("Rpns0:" + gem5.rpns());
        System.out.println("Rpns1:" + gem5.rpns());
    }

    static {
        System.loadLibrary("gem5OpJni");
    }
}

When building you need to make sure classpath include gem5OpJni.jar:
javac -classpath $CLASSPATH:/path/to/gem5OpJni.jar HelloWorld.java

and when running you need to make sure both the java and library path are set:
java -classpath $CLASSPATH:/path/to/gem5OpJni.jar -Djava.library.path=/path/to/libgem5OpJni.so HelloWorld
2011-09-13 12:06:13 -05:00
Ali Saidi
28a2236ec1 O3: Update stats for new ordering fix. 2011-09-13 12:58:09 -04:00
Ali Saidi
649c239cee LSQ: Only trigger a memory violation with a load/load if the value changes.
Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
2011-09-13 12:58:08 -04:00
Deyuan Guo
bb921b1459 MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote
debugging.

Testing:

Build gem5 for MIPS_SE and make gem5 wait at beginning:
modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc;
scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU
----
Build GDB-7.3 mips-cross:
./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/
make
make install
----
Run:
./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches
./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello
(gdb) target remote :7000
(gdb) info registers
(gdb) disassemble
(gdb) si
(gdb) break main
(gdb) c
(gdb) quit
Testing done.
2011-09-10 03:45:25 -07:00
Gabe Black
6a2b223112 PseudoInst: Add compiler guards to pseudo_inst.hh. 2011-09-10 02:31:15 -07:00
Gabe Black
49a7ed0397 StaticInst: Merge StaticInst and StaticInstBase.
Having two StaticInst classes, one nominally ISA dependent and the other ISA
dependent, has not been historically useful and makes the StaticInst class
more complicated that it needs to be. This change merges StaticInstBase into
StaticInst.
2011-09-09 02:40:11 -07:00
Gabe Black
b7b545bc38 Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
2011-09-09 02:30:01 -07:00
Gabe Black
c5fd6f4fec MIPS: Update MIPS stats for cleaned up operand checks. 2011-09-09 01:35:05 -07:00
Gabe Black
a1ad9e652a Stack: Tidy up some comments, a warning, and make stack extension consistent.
Do some minor cleanup of some recently added comments, a warning, and change
other instances of stack extension to be like what's now being done for x86.
2011-09-09 01:01:43 -07:00
Gabe Black
f370ac5c18 ISA parser: Don't look for operands in strings. 2011-09-08 03:21:14 -07:00
Gabe Black
f4dc64655f ISA parser: Match /* */ and // style comments.
Comments should not be scanned for operands, and we should look for both /* */
style and // style.
2011-09-08 03:20:05 -07:00
Gabe Black
87d687e242 X86: Make sure instruction flags are set properly even on 32 bit machines.
The way flag bits were being set for microops in x86 ended up implicitly
calling the bitset constructor which was truncating flags beyond the width of
an unsigned long. This change sets the bits in chunks which are always small
enough to avoid being truncated. On 64 bit machines this should reduce to be
the same as before, and on 32 bit machines it should work properly and not be
unreasonably inefficient.
2011-09-05 18:36:26 -07:00
Gabe Black
3bd0b9654c X86,TLB: Make sure the "delayedResponse" variable is always set.
When an instruction is translated in the x86 TLB, a variable called
delayedResponse is passed back and forth which tracks whether a translation
could be completed immediately, or if there's going to be callback that will
finish things up. If a read was to the internal memory space, memory mapped
registers used to implement things like MSRs, the function hadn't yet gotten
to where delayedResponse was set to false, it's default. That meant that the
value was never set, and the TLB could start waiting for a callback that would
never come. This change simply moves the assignment to above where control
can divert to translateInt().
2011-09-05 02:48:57 -07:00
Lisa Hsu
365966304e TLB: comments and a helpful warning.
Nothing big here, but when you have an address that is not in the page table request to be allocated, if it falls outside of the maximum stack range all you get is a page fault and you don't know why.  Add a little warn() to explain it a bit.  Also add some comments and alter logic a little so that you don't totally ignore the return value of checkAndAllocNextPage().
2011-09-02 17:04:00 -07:00
Lisa Hsu
f6a2ef22ff Fix build for gcc-4.2 opt/fast
Even though the code is safe, compiler flags a warning here, which are treated as errors for fast/opt. I know it's redundant but it has no side effects and fixes the compile.
2011-09-01 15:25:54 -07:00
Lisa Hsu
ae12ae3023 Functional Accesses: Update states to support Broadcast/Snooping protocols.
In the current implementation of Functional Accesses, it's very hard to
implement broadcast or snooping protocols where the memory has no idea if it
has exclusive access to a cache block or not. Without this knowledge, making
sure the RW vs. RO permissions are right are next to impossible. So we add a
new state called Backing_Store to enable the conveyance that this is the backup
storage for a block, so that it can be written if it is the only possibly RW
block in the system, or written even if there is another RW block in the
system, without causing problems.

Also, a small change to actually set the m_name field for each Controller so
that debugging can be easier. Now you can access a controller's name just by
controller->getName().
2011-09-01 11:41:44 -07:00
Nilay Vaish
ebda5c14a5 SLICC: Pass arguments by reference
Arguments to functions were being passed by value. This patch
changes SLICC so that arguments are passed by reference.
2011-08-29 06:34:40 -05:00
Nilay Vaish
1bbca50491 Ruby: Remove some unused code 2011-08-29 05:10:23 -05:00
Nilay Vaish
a08cc94936 Ruby: Eliminate modulo op for computing set size. 2011-08-26 12:27:58 -05:00
Ali Saidi
ba265abbfd ARM: Add some MP regressions and clean up the disk images and kernels a bit 2011-08-19 15:08:09 -05:00
Ali Saidi
c9d5985b82 ARM: Mark some variables uncacheable until boot all CPUs are enabled.
There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).
2011-08-19 15:08:08 -05:00
Ali Saidi
c9c2d979b8 Mem: Put prefetcher notify call before packet is deleted. 2011-08-19 15:08:08 -05:00
Ali Saidi
2fd2b44b86 ARM: Add VExpress_E support with PCIe to gem5 2011-08-19 15:08:08 -05:00
Ali Saidi
d2a0a2ec22 ARM: Add support for Versatile Express boards 2011-08-19 15:08:08 -05:00
Ali Saidi
23755eb434 ARM: Make GIC function that should only be called by GIC protected. 2011-08-19 15:08:08 -05:00
Ali Saidi
243223ae63 IDE: Fix issues with new PIIX kernel driver and our model.
The driver can read the IDE config register as a 32 bit register since
some adapters use bit 18 as a disable channel bit. If the size isn't
set in a PRD it should be 64K according to the SPEC (and driver) not
128K.
2011-08-19 15:08:08 -05:00
Ali Saidi
999cd8aef5 StoreSet: Update stats for store-set clearing 2011-08-19 15:08:08 -05:00
Ali Saidi
b94f841969 ARM: Add support for DIV/SDIV instructions. 2011-08-19 15:08:07 -05:00
Ali Saidi
b6203360ef LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
This patch improves performance by as much as 10% on some spec benchmarks.
2011-08-19 15:08:07 -05:00
Geoffrey Blake
5f425b8bd1 Fix bugs due to interaction between SEV instructions and O3 pipeline
SEV instructions were originally implemented to cause asynchronous squashes
via the generateTCSquash() function in the O3 pipeline when updating the
SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system
that would lead to a pipeline either going inactive indefinitely or not being
able to commit squashed instructions. Fixed SEV instructions to behave like
interrupts and cause synchronous sqaushes inside the pipeline, eliminating
the race conditions. Also fixed up the semantics of the WFE instruction to
behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1
or unmasked interrupts are pending.
2011-08-19 15:08:07 -05:00
Ali Saidi
f125ef22b9 O3: Update stats for LSQ changes. 2011-08-19 15:08:06 -05:00
Mrinmoy Ghosh
d0e0485902 LSQ: Add some better dprintfs for storeset predictor. 2011-08-19 15:08:05 -05:00
Mrinmoy Ghosh
0db95030fc LSQ: Fix a few issues with the storeset predictor.
Two issues are fixed in this patch:
1. The load and store pc passed to the predictor are passed in reverse order.
2. The flag indicating that a barrier is inflight was never cleared when
   the barrier was squashed instead of committed. This made all load insts
   dependent on a non-existent barrier in-flight.
2011-08-19 15:08:05 -05:00
Thomas Grass
3f1ae35c6d Stats: Add a sparse histogram stat object. 2011-08-19 15:08:05 -05:00
Giacomo Gabrielli
676a530b77 O3: Squash the violator and younger instructions instead not all insts.
Change the way instructions are squashed on memory ordering violations
to squash the violator and younger instructions, not all instructions
that are younger than the instruction they violated (no reason to throw
away valid work).
2011-08-19 15:08:05 -05:00
Geoffrey Blake
f778c46b5e ARM: Add per-cpu local timers for ARM.
Cortex-A9 processors can have a local timer and watchdog counter. It
is enabled by default in Linux and up to this point we've had to disable
them since a model wasn't available. This change allows a default
MP ARM Linux configuration to boot.
2011-08-19 15:08:05 -05:00
Prakash Ramrakhani
efd91d2237 ARM: Add per-processor interrupt support to GIC. 2011-08-19 15:08:05 -05:00
Ali Saidi
9b356adf54 ARM: Fix a memory leak with the table walker. 2011-08-19 15:08:05 -05:00
Ali Saidi
6779bd3e5d Prefetcher: Fix some memory leaks with the prefetcher. 2011-08-19 15:08:05 -05:00
Ali Saidi
b3a058f220 ARM: quiet what can be a very noise CLCD controller. 2011-08-19 15:08:05 -05:00
Gabe Black
f2c89a01d1 InOrder: Make cache_unit.hh include hashmap.hh explicitly, not transitively. 2011-08-16 02:47:15 -07:00
Gabe Black
78a4636a13 O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively. 2011-08-16 02:46:57 -07:00
Nilay Vaish
769c1844f0 Ruby: Initialize some variables. 2011-08-15 12:56:47 -05:00
Gabe Black
cbf7982081 X86: Add an X86_FS o3 regression. 2011-08-14 18:34:17 -07:00
Gabe Black
0e6dc00497 O3: When squashing, restore the macroop that should be used for fetching. 2011-08-14 17:41:34 -07:00
Gabe Black
ec204f003c O3: Add a pointer to the macroop for a microop in the dyninst. 2011-08-14 04:08:14 -07:00
Gabe Black
a81d4a8fcd Stats: Small update to stats for change to x86 inst flags. 2011-08-13 23:03:21 -07:00
Gabe Black
1b9de61a71 X86: Use IsSquashAfter if an instruction could affect fetch translation.
Control register operands are set up so that writing to them is serialize
after, serialize before, and non-speculative. These are probably overboard,
but they should usually be safe. Unfortunately there are times when even these
aren't enough. If an instruction modifies state that affects fetch, later
serialized instructions which come after it might have already gone through
fetch and decode by the time it commits. These instructions may have been
translated incorrectly or interpretted incorrectly and need to be destroyed.
This change modifies instructions which will or may have this behavior so that
they use the IsSquashAfter flag when necessary.
2011-08-13 23:03:11 -07:00
Gabe Black
e0043f8dbe O3: At the end of an instruction, force fetchAddr to something sensible.
It's possible (though until now very unlikely) for fetchAddr to get out of
sync with the actual PC of the current instruction. This change forcefull
resets fetchAddr at the end of every instruction.
2011-08-13 13:36:37 -07:00